公开(公告)号：US10447507B1

公开(公告)日：2019-10-15

申请号：US16172591

申请日：2018-10-26

Applicant: NXP B.V.

Inventor： Xu Zhang ,  Soon-Gil Jung ,  Ahmad Yazdi

IPC: H03L7/08 ,  H04L25/03

Abstract: Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.

公开(公告)号：US10432432B1

公开(公告)日：2019-10-01

申请号：US16047824

申请日：2018-07-27

Applicant: NXP B.V.

Inventor： Xiaoqun Liu ,  Siamak Delshadpour ,  Ahmad Yazdi

IPC: H04L25/03 ,  H04B3/46 ,  H03K5/24

Abstract: An electronic circuit, including an equalizer circuit to input a differential signal, a rectifier circuit to receive the differential signal and output a first current and a second current, a replica circuit to receive a differential threshold signal and output a third current and a fourth current to compensate for PVT variations in the first and second currents, and a comparator circuit configured to compare a differential voltage generated based on the first, second, third, and fourth currents to determine a loss of signal event of the electronic circuit.

公开(公告)号：US09729132B1

公开(公告)日：2017-08-08

申请号：US15222561

申请日：2016-07-28

Applicant: NXP B.V.

Inventor： Xu Zhang ,  Siamak Delshadpour ,  Ahmad Yazdi

IPC: G01R19/00 ,  H03K5/24

CPC classification number: H03K5/2481 ,  G01R19/04 ,  H03G3/341

Abstract: A squelch detector, including: an input configured to receive an input signal; a peak detector connected to the input configured to detect a maximum value of the input signal wherein the peak detector includes a refresh input configured to receive a refresh signal to refresh the output of the peak detector, a valley detector connected to the input configured to detect a minimum value of the input signal wherein the valley detector includes a refresh input configured to receive the refresh signal to refresh the output of the valley detector, and a comparator including a first signal input connected to an output of the peak detector, a second input connected to an output of the valley detector, and a first reference input, wherein the comparator is configured to compare a difference between an output of the peak detector and an output of the valley detector and a reference value received at the first reference input and configured to produce an output based upon the comparison.