公开(公告)号：US10978444B2

公开(公告)日：2021-04-13

申请号：US16135075

申请日：2018-09-19

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad

IPC: H01L27/02 ,  H02H9/04

Abstract: A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event.

公开(公告)号：US12021077B2

公开(公告)日：2024-06-25

申请号：US18166860

申请日：2023-02-09

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Mikhail Yurievich Semenov ,  Yury Vladimirovich Alymov ,  Elena Valentinovna Somova

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0281 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H02H9/045

Abstract: Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

公开(公告)号：US20230115302A1

公开(公告)日：2023-04-13

申请号：US17450179

申请日：2021-10-07

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Denizhan Karaca

IPC: H01L27/02

Abstract: Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

公开(公告)号：US10826290B2

公开(公告)日：2020-11-03

申请号：US15390037

申请日：2016-12-23

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Madan Mohan Reddy Vemula

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, the ESD protection circuit is connected between a VDD rail and a VSS rail and includes an internal floating ESD rail located between the VDD rail and the VSS rail, I/O pins connected between the internal floating ESD rail and the VSS rail, ESD diodes corresponding to at least one I/O pin, an internal bias cell corresponding to an I/O pin and configured to short the corresponding I/O pin to the internal floating ESD rail when the I/O pin is pulled high, and an internal bias cell corresponding to a VDD pin of the VDD rail and configured to short the VDD rail to the internal floating ESD rail when the VDD pin is pulled high.

公开(公告)号：US20180183233A1

公开(公告)日：2018-06-28

申请号：US15390037

申请日：2016-12-23

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Madan Mohan Reddy Vemula

IPC: H02H9/04

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, the ESD protection circuit is connected between a VDD rail and a VSS rail and includes an internal floating ESD rail located between the VDD rail and the VSS rail, I/O pins connected between the internal floating ESD rail and the VSS rail, ESD diodes corresponding to at least one I/O pin, an internal bias cell corresponding to an I/O pin and configured to short the corresponding I/O pin to the internal floating ESD rail when the I/O pin is pulled high, and an internal bias cell corresponding to a VDD pin of the VDD rail and configured to short the VDD rail to the internal floating ESD rail when the VDD pin is pulled high.