公开(公告)号：US12108640B2

公开(公告)日：2024-10-01

申请号：US17418810

申请日：2020-11-03

Applicant: Beijing BOE Technology Development Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Hongfei Cheng ,  Xueguang Hao

IPC: H10K59/131 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/02

CPC classification number: H10K59/131 ,  G02F1/136204 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/0266 ,  H01L27/0288

Abstract: Provided is an array substrate, including: a first conductive wire, a second conductive wire and a first electrostatic protection unit, wherein the first electrostatic protection unit comprises a first thin-film transistor and a first capacitor; wherein a gate of the first thin-film transistor is suspended and is connected to a first electrode of the first thin-film transistor via the first capacitor, the first electrode of the thin-film transistor is connected to the first conductive wire, and a second electrode of the first thin-film transistor is connected to the second conductive wire.

公开(公告)号：US20240304614A1

公开(公告)日：2024-09-12

申请号：US18651586

申请日：2024-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Han LIN ,  Meng-Sheng CHANG

IPC: H01L27/02 ,  H01L21/82

CPC classification number: H01L27/0288 ,  H01L21/82 ,  H01L27/0218

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a shallow trench isolation, and a capacitor. The STI is in the semiconductor substrate. The capacitor is over the STI. The capacitor includes first a dummy gate strip, a second dummy gate strip extending in parallel with the first dummy gate strip, a plurality of first metal contacts landing on the first dummy gate strip, and a plurality of second metal contacts landing on the second dummy gate strip.

公开(公告)号：US12002802B2

公开(公告)日：2024-06-04

申请号：US18158452

申请日：2023-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Han Lin ,  Meng-Sheng Chang

IPC: H01L29/40 ,  H01L21/82 ,  H01L27/02

CPC classification number: H01L27/0288 ,  H01L21/82 ,  H01L27/0218

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a shallow trench isolation (STI) region, and a capacitor. The STI region is embedded in the semiconductor substrate. The capacitor includes first and second conductive stacks. The first conductive stack includes a first dummy gate strip disposed entirely within the STI region and a plurality of first metal dummy gate contacts landing on the first metal capacitor strip. The second conductive stack includes a second dummy gate strip disposed entirely within the STI region and extending in parallel with the first dummy gate strip, and a plurality of second dummy gate contacts landing on the second dummy gate strip, wherein the first conductive stack is electrically isolated from the second conductive stack.

公开(公告)号：US11990468B2

公开(公告)日：2024-05-21

申请号：US17821615

申请日：2022-08-23

Applicant: Infineon Technologies AG

Inventor： Valentyn Solomko ,  Semen Syroiezhin ,  Mirko Scholz

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L27/0255 ,  H01L27/0266 ,  H02H9/04

Abstract: An RF switch device includes transistors coupled in series forming an RF conductive current path; a first resistive bias network forming a DC conductive bias path between gate nodes of the plurality of transistors; and a first ESD bias component coupled between the RF conductive current path and the first resistive bias network, wherein the first ESD bias component provides a DC conductive path between the RF conductive current path of the RF switch device and the first resistive bias network during an ESD event.

公开(公告)号：US11973342B2

公开(公告)日：2024-04-30

申请号：US18125465

申请日：2023-03-23

Applicant: Mavagail Technology, LLC

Inventor： Darryl G. Walker

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/0292 ,  H01L27/0296

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

公开(公告)号：US11936179B2

公开(公告)日：2024-03-19

申请号：US17810235

申请日：2022-06-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Pan Mao ,  Yingtao Zhang ,  Junjie Liu ,  Lingxin Zhu ,  Bin Song ,  Qi'an Xu ,  Tieh-Chiang Wu

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0288 ,  H01L27/0292

Abstract: A discharge unit is connected to a power pad, a ground pad, and an I/O pad, and can discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad. The discharge unit includes a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad. The first discharge unit and/or the second discharge unit can discharge electrostatic charges on different pads, respectively.

公开(公告)号：US20240088137A1

公开(公告)日：2024-03-14

申请号：US18513544

申请日：2023-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao-Yi HUNG ,  Wun-Jie LIN ,  Jam-Wem LEE ,  Kuo-Ji CHEN

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L27/0255 ,  H01L27/0266 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

公开(公告)号：US20240088135A1

公开(公告)日：2024-03-14

申请号：US18513254

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung YEH

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0288 ,  H02H9/046

Abstract: An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.

公开(公告)号：US11923764B1

公开(公告)日：2024-03-05

申请号：US17885461

申请日：2022-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Liang Zhang

IPC: H02M1/32 ,  H01L27/02 ,  H02M1/00

CPC classification number: H02M1/322 ,  H01L27/0288 ,  H02M1/0009 ,  H02M1/0012

Abstract: In one example, a circuit comprises: a controller, an electrostatic discharge (ESD) circuit, and a driver circuit. The controller has a driver control output. The ESD circuit has a driver control input and an ESD output, the driver control input coupled to the driver control output. The driver circuit has a driver input and a driver output, the driver input coupled to the ESD output.

公开(公告)号：US11916063B2

公开(公告)日：2024-02-27

申请号：US17397583

申请日：2021-08-09

Applicant: SK hynix Inc.

Inventor： Joung Cheul Choi ,  Chang Seok Song

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/74

CPC classification number: H01L27/0277 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0274 ,  H01L27/0288 ,  H01L27/0292 ,  H01L29/7408 ,  H02H9/046 ,  H01L29/7404

Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.