-
公开(公告)号：US12021076B2
公开(公告)日：2024-06-25
申请号：US17450179
申请日：2021-10-07
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Denizhan Karaca
IPC: H01L27/02
CPC classification number: H01L27/0266 , H01L27/0255
Abstract: Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.
-
公开(公告)号：US20220359318A1
公开(公告)日：2022-11-10
申请号：US17661729
申请日：2022-05-02
Applicant: NXP B.V.
Inventor： Denizhan Karaca , Gijs Jan de Raad , Marcus van der Vossen , Eric Thomas
IPC: H01L21/66 , H01L23/60 , H01L23/66 , H03K17/0812
Abstract: An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.
-
公开(公告)号：US20240405013A1
公开(公告)日：2024-12-05
申请号：US18325503
申请日：2023-05-30
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Guido Wouter Willem Quax
IPC: H01L27/02
Abstract: An electrostatic discharge circuit includes two or more GGNMOS transistors where each transistor includes two types of body contact regions. Body contact regions of one type are non substrate isolated from body contact regions of the other type. A body contact region of one type is electrically coupled to the source region of its transistor and a body contact region of the other type is electrically connected to at least one other body contact region of the same type of another GGNMOS transistor.
-
公开(公告)号：US20220209527A1
公开(公告)日：2022-06-30
申请号：US17332619
申请日：2021-05-27
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Junfei Yu , Rongrong Tang , Haojing Wu
Abstract: Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.
-
5.发明授权公开(公告)号：US10366974B2
公开(公告)日：2019-07-30
申请号：US15595068
申请日：2017-05-15
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Da-Wei Lai
Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.
-
Patent Agency Ranking
公开(公告)号：US11532936B2
公开(公告)日：2022-12-20
申请号：US17332619
申请日：2021-05-27
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Junfei Yu , Rongrong Tang , Haojing Wu
Abstract: Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.
-
公开(公告)号：US20210143146A1
公开(公告)日：2021-05-13
申请号：US16677221
申请日：2019-11-07
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad
Abstract: An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.
-
8.发明申请公开(公告)号：US20180331090A1
公开(公告)日：2018-11-15
申请号：US15595068
申请日：2017-05-15
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Da-Wei Lai
CPC classification number: H01L27/0248 , H01L27/0251 , H01L27/0259 , H01L27/0262 , H01L29/7833 , H02H9/046 , H05K9/0067
Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.
-
公开(公告)号：US20230282637A1
公开(公告)日：2023-09-07
申请号：US18166860
申请日：2023-02-09
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad , Mikhail Yurievich Semenov , Yury Vladimirovich Alymov , Elena Valentinovna Somova
CPC classification number: H01L27/0281 , H02H9/045 , H01L27/0255 , H01L27/0296 , H01L27/0288
Abstract: Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.
-
公开(公告)号：US11251176B2
公开(公告)日：2022-02-15
申请号：US16677221
申请日：2019-11-07
Applicant: NXP B.V.
Inventor： Gijs Jan de Raad
Abstract: An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.019 seconds)
