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公开(公告)号：US5239631A
公开(公告)日：1993-08-24
申请号：US778041
申请日：1991-10-15
IPC分类号： G06F13/18 , G06F13/30 , G06F13/362
CPC分类号： G06F13/3625 , G06F13/30
摘要： An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second time, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.
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12.发明授权Expandable high performance FIFO design which includes memory cells having respective cell multiplexors 失效可扩展的高性能FIFO设计，其包括具有相应的单元复用器的存储单元
公开(公告)号：US5551009A
公开(公告)日：1996-08-27
申请号：US134504
申请日：1993-10-12
CPC分类号： G06F5/065
摘要： An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.
摘要翻译： 公开了具有输入和输出转向电路以及内部移位能力的单元的布置，其有利地提供可以连续的时钟周期写入和读取的第一进/出（FIFO）寄存器电路。 FIFO寄存器电路具有自包含FIFO单元的布置，每个单元包含其自己的输入多路复用器和控制电路。
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公开(公告)号：US20070204091A1
公开(公告)日：2007-08-30
申请号：US11557119
申请日：2006-11-07
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F13/4022
摘要： A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.
摘要翻译： 一种用于在处理系统中传送数据的处理系统和方法。 处理系统包括总线主控装置，多个从设备和配置成在从设备之间切换总线主控装置的总线互连。 每个从设备具有多个地址。 总线互连包括DMA控制器，其被配置为响应于来自总线主控装置的单个总线命令，将数据从地址的第一个地址传送到第二个地址。
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公开(公告)号：US08675679B2
公开(公告)日：2014-03-18
申请号：US13330734
申请日：2011-12-20
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.
摘要翻译： 公开了一种通过总线进行通信的方法。 总线包括写地址通道，写通道和读地址通道。 该方法包括经由写入地址信道从发送设备发送地址到接收设备。 该方法还包括经由读取地址信道经由写入信道和有效载荷的另一部分经由读取地址信道同时将一部分有效负载发送到接收设备。 当经由总线同时发送有效负载的多个连续部分时，发送设备被配置为通过经由写入通道发送多个连续部分的第一顺序部分来通过读取地址信道给予写入信道的数据排序偏好，并且发送 多个顺序部分的后续顺序部分经由读地址信道。
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公开(公告)号：US08107492B2
公开(公告)日：2012-01-31
申请号：US11468908
申请日：2006-08-31
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
摘要翻译： 公开了一种用于通过总线在处理系统中通信的处理系统和方法。 处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是 还被配置为将所述有效负载的第一部分写入所述第一信道上的所述接收设备，并且将所述有效载荷的第二部分写入所述第三信道上的接收设备。
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公开(公告)号：US20070233904A1
公开(公告)日：2007-10-04
申请号：US11468933
申请日：2006-08-31
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译： 公开了一种用于通过总线在处理系统中通信的处理系统和方法。 处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是 还被配置为在所述第一和第三信道之间选择以将有效负载写入所述接收设备。
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公开(公告)号：US08108563B2
公开(公告)日：2012-01-31
申请号：US11468933
申请日：2006-08-31
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译： 公开了一种用于通过总线在处理系统中通信的处理系统和方法。 处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是 还被配置为在所述第一和第三信道之间选择以将有效负载写入所述接收设备。
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公开(公告)号：US07933289B2
公开(公告)日：2011-04-26
申请号：US11468908
申请日：2006-08-31
IPC分类号： H04J3/00
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
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公开(公告)号：US07249210B2
公开(公告)日：2007-07-24
申请号：US11070338
申请日：2005-03-01
CPC分类号： G06F13/362
摘要： A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.
摘要翻译： 处理系统中的总线仲裁方案。 处理系统包括总线，耦合到总线的多个处理器和总线仲裁器。 总线仲裁器可以向第一层中的每个处理器分配第一层权重，并且向第二层中的每个处理器分配第二层权重。 总线仲裁器可以基于所分配的第二层权重在总线间隔的初始部分期间顺序地授予对一个或多个处理器的总线访问，并且在总线间隔的初始部分中响应地授予总线对任何一个处理器的访问 来自所述任何一个具有第一层权重的处理器的请求。 当多个处理器请求访问总线时，总线仲裁器可以向最高级别中具有最高权重的请求处理器授予总线访问。
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20.发明授权Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components 失效用于集成电路电子元件的边界扫描旁路电路和包含这样的电路和部件的电路板
公开(公告)号：US5615217A
公开(公告)日：1997-03-25
申请号：US352080
申请日：1994-12-01
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318558
摘要： A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.
摘要翻译： 一种用于在电子部件的功能操作期间旁路边界扫描单元的方法和装置在电子部件的正常功能操作期间向边界扫描旁路电路提供分量输出信号（例如数据信号）。 分量输出信号在旁路电路中被复用在边界扫描测试期间发生的测试结果信号。 在电子部件的功能操作期间，分量输出信号被选择并提供给由电子部件的时钟信号的转变而被定时的输出锁存器。 通过在正常操作期间绕过边界扫描单元周围的分量输出信号，避免了在分量的时钟信号转变之后通过分量输出信号的多路复用器的遍历，从而减少了片外延迟。
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