公开(公告)号：US5555413A

公开(公告)日：1996-09-10

申请号：US390610

申请日：1995-02-17

申请人： Terence Lohman ,  Mark G. Noll ,  Jose A. Olive ,  Roberto V. Perez

发明人： Terence Lohman ,  Mark G. Noll ,  Jose A. Olive ,  Roberto V. Perez

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4812

摘要： A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

摘要翻译： 具有响应于在中断请求处接收到信号而服务中断的处理器的计算机系统具有耦合到处理器的第一设备和第二设备。 第一设备能够发送包括边缘转换的第一中断请求信号。 第二设备能够发送包括电平断言的第二中断请求信号。 中断处理程序耦合到处理器和第一和第二设备，中断处理程序接收第一和第二中断请求信号作为输入，并且根据预定标准将处理器的第一和第二中断请求信号作为输出提供给处理器 第一和第二中断请求信号具有相同的优先级。

公开(公告)号：US5539912A

公开(公告)日：1996-07-23

申请号：US279308

申请日：1994-07-22

申请人： Grant L. Clarke, Jr. ,  Peter J. Klim ,  Mark G. Noll ,  Jose A. Olive

发明人： Grant L. Clarke, Jr. ,  Peter J. Klim ,  Mark G. Noll ,  Jose A. Olive

IPC分类号： G06F12/06 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4243 ,  G06F12/0684

摘要： A personal computer has two possible memory sizes differing by the maximum number SIMMs that can be installed. Each SIMM stores presence detect bits indicating the size and speed of the SIMM. An I/O controller includes a memory detect port which is used to read the presence detect bits from the SIMMs. The controller further includes a logic circuit that is set in accordance with the memory size to selectively control driving the presence detect bits or empty socket bits onto a data bus.

摘要翻译： 个人计算机有两种可能的存储容量大小，可以通过最大数量的SIMM来安装。 每个SIMM存储指示SIMM的大小和速度的存在检测位。 I / O控制器包括用于从SIMM读取存在检测位的存储器检测端口。 控制器还包括根据存储器大小设置的逻辑电路，以选择性地控制将存在检测位或空插座位驱动到数据总线上。

公开(公告)号：US5615217A

公开(公告)日：1997-03-25

申请号：US352080

申请日：1994-12-01

申请人： Rick L. Horne ,  Terence J. Lohman ,  Mark G. Noll ,  Jose A. Olive ,  Roberto V. Perez

发明人： Rick L. Horne ,  Terence J. Lohman ,  Mark G. Noll ,  Jose A. Olive ,  Roberto V. Perez

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318558

摘要： A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.

摘要翻译： 一种用于在电子部件的功能操作期间旁路边界扫描单元的方法和装置在电子部件的正常功能操作期间向边界扫描旁路电路提供分量输出信号（例如数据信号）。 分量输出信号在旁路电路中被复用在边界扫描测试期间发生的测试结果信号。 在电子部件的功能操作期间，分量输出信号被选择并提供给由电子部件的时钟信号的转变而被定时的输出锁存器。 通过在正常操作期间绕过边界扫描单元周围的分量输出信号，避免了在分量的时钟信号转变之后通过分量输出信号的多路复用器的遍历，从而减少了片外延迟。

公开(公告)号：US5608897A

公开(公告)日：1997-03-04

申请号：US667767

申请日：1996-06-21

申请人： Margaret Claffey-Cohen ,  Mark G. Noll ,  Jose A. Olive ,  Roberto V. Perez ,  James P. Ward

发明人： Margaret Claffey-Cohen ,  Mark G. Noll ,  Jose A. Olive ,  Roberto V. Perez ,  James P. Ward

IPC分类号： G06F1/14

CPC分类号： G06F1/14

摘要： A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.

摘要翻译： 提供了一种用于计算机系统的超时机制，包括时钟线性反馈移位寄存器和可编程比较机制。 线性反馈移位寄存器包括串联连接的一系列锁存器，并且响应于接收到的中断信号（i）在存在中断信号的情况下依次增量地计数，以在中断信号的输出端提供不同的二进制向量阵列 按序列中的每个计数锁存，以及（ii）在不存在中断信号的情况下复位到特定的二进制向量阵列。 比较机构响应于线性反馈移位寄存器输出预定计数并在锁存器的输出处输出相应的预定二进制向量阵列来输出超时命令。 超时机制使用最小量的组合逻辑，同时允许在任何多个时钟周期之后检测到中断信号后发出超时命令。