Developing assembly, developer quantity control blade and process for manufacturing developer quantity control blade
    11.
    发明申请
    Developing assembly, developer quantity control blade and process for manufacturing developer quantity control blade 失效
    开发组件,开发者数量控制刀片和制造开发者数量控制刀片的过程

    公开(公告)号:US20050111885A1

    公开(公告)日:2005-05-26

    申请号:US11031068

    申请日:2005-01-10

    申请人: Toru Ishigaki

    发明人: Toru Ishigaki

    IPC分类号: G03G15/08

    CPC分类号: G03G15/0812

    摘要: In a developing assembly comprising a developer-carrying member and a developer quantity control blade kept in pressure contact with the developer-carrying member, the developer-carrying member has a deformation percentage D of 0.5% or less in the direction of pressure contact, and the developer quantity control blade has a ten-point average roughness Rz of from 0.3 μm to 20 μm at its surface on the side kept in contact with the developer-carrying member (a charge control face). The developing assembly can prevent faulty images such as lines and uneven images due to the deformation of developer-carrying member even though any deformation due to the pressure contact of the developer quantity control blade has taken place in the developer-carrying member while the developing assembly is stopped.

    摘要翻译: 在显影剂组件中,显影剂承载元件与显影剂承载元件保持压力接触的显影剂承载元件和显影剂量控制刮刀,显影剂承载元件在压接方向上的变形百分数D为0.5%或更小, 显影剂量控制刮板在与显影剂承载构件(充电控制面)保持接触的一侧的表面上的十点平均粗糙度Rz为0.3μm至20μm。 显影组件可以防止由于显影剂承载构件的变形而引起的显影剂承载构件的变形导致的错误图像,例如线和不均匀的图像,即使显影组件中显影剂承载构件发生由于显影剂量控制刮板的压力接触而导致的任何变形 被停止

    Developer level control blade and process for manufacturing developer level control blade
    13.
    发明授权
    Developer level control blade and process for manufacturing developer level control blade 有权
    开发者级别控制刀片和制造开发者级别控制刀片的过程

    公开(公告)号:US08095050B2

    公开(公告)日:2012-01-10

    申请号:US12051526

    申请日:2008-03-19

    IPC分类号: G03G15/09

    摘要: A developer level control blade is provided which can form a developer layer on a developer carrying member in a proper thickness and in a uniform state and can keep the developer, in particular, color toner particles from melt-adhering to the charge control face so that faulty images such as lines and non-uniformity can be kept from occurring. Also provided is a process for manufacturing this developer level control blade. The process for manufacturing the developer level control blade is characterized by having the steps of extruding a blade member material melted to liquefy, covering therewith a support member thin-plate metal member at an edge portion thereof to join the both together, and cooling the blade member material to solidify, followed by cutting in a preset length.

    摘要翻译: 提供了一种显影剂级控制刀片,其可以在适当厚度和均匀状态下在显影剂承载构件上形成显影剂层,并且可以使显影剂,特别是彩色调色剂颗粒熔化粘附到电荷控制面,从而 可以防止诸如线和不均匀性的故障图像发生。 还提供了用于制造该显影剂液位控制刮刀的过程。 制造显影剂液位控制叶片的方法的特征在于具有将熔融液化的叶片构件材料挤出的步骤,在其边缘部分覆盖支撑构件薄板金属构件,以将两者结合在一起,并冷却叶片 构件材料固化,然后以预设长度切割。

    PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY
    14.
    发明申请
    PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY 有权
    程序电压补偿与字线偏置更改为在存储器中禁止充电捕获

    公开(公告)号:US20110026331A1

    公开(公告)日:2011-02-03

    申请号:US12512181

    申请日:2009-07-30

    IPC分类号: G11C16/04

    CPC分类号: G11C16/0483 G11C16/3404

    摘要: Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.

    摘要翻译: 在所选择的字线的编程操作期间,在非易失性存储系统中,通过在与所选择的字线相邻的字线上最初使用具有较低幅度的通过电压来减少编程干扰。 这有助于减少浮栅边缘的电荷捕获,这可以通过增加编程擦除周期来扩大阈值电压分布。 当将较高幅度的编程脉冲施加到所选字线时,通过电压切换到较高电平以提供足够量的通道升压。 可以通过施加指定的编程脉冲或者通过跟踪下部状态存储元件直到达到目标验证电平来触发切换到较高通过电压。 当通过电压升高时,编程电压的幅度降低,从通过电压的变化中消除所选存储元件的电容耦合。

    Compensating for coupling during read operations in non-volatile storage
    15.
    发明授权
    Compensating for coupling during read operations in non-volatile storage 有权
    补偿在非易失性存储器中读取操作期间的耦合

    公开(公告)号:US07876611B2

    公开(公告)日:2011-01-25

    申请号:US12188629

    申请日:2008-08-08

    IPC分类号: G11C11/34

    摘要: Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

    摘要翻译: 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态,并且在随后的精细读取期间,基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时,使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿,并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻存储元件。

    Semiconductor device having reduced field oxide recess and method of fabrication
    17.
    发明授权
    Semiconductor device having reduced field oxide recess and method of fabrication 失效
    具有减小的场氧化物凹陷的半导体器件和制造方法

    公开(公告)号:US06492229B2

    公开(公告)日:2002-12-10

    申请号:US09729516

    申请日:2000-12-04

    IPC分类号: H01L218247

    摘要: A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.

    摘要翻译: 公开了一种具有减小的场氧化物凹陷和制造方法的半导体器件。 制造半导体器件的方法是通过在场氧化之后对衬底进行HF浸渍法,然后进行选择栅极氧化而开始的。 此后,进行核心植入和场植入。 在植入物之后,沉积隧道氧化物掩模。 然后在不被隧道氧化物掩模覆盖的区域中蚀刻选择栅极氧化物,并且执行隧道氧化。

    Program voltage compensation with word line bias change to suppress charge trapping in memory
    18.
    发明授权
    Program voltage compensation with word line bias change to suppress charge trapping in memory 有权
    程序电压补偿用字线偏置改变,以抑制存储器中的电荷捕获

    公开(公告)号:US07995394B2

    公开(公告)日:2011-08-09

    申请号:US12512181

    申请日:2009-07-30

    IPC分类号: G11C11/34

    CPC分类号: G11C16/0483 G11C16/3404

    摘要: Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.

    摘要翻译: 在所选择的字线的编程操作期间,在非易失性存储系统中,通过在与所选择的字线相邻的字线上最初使用具有较低幅度的通过电压来减少编程干扰。 这有助于减少浮栅边缘的电荷捕获,这可以通过增加编程擦除周期来扩大阈值电压分布。 当将较高幅度的编程脉冲施加到所选字线时,通过电压切换到较高电平以提供足够量的通道升压。 可以通过施加指定的编程脉冲或者通过跟踪下部状态存储元件直到达到目标验证电平来触发切换到较高通过电压。 当通过电压升高时,编程电压的幅度降低,从通过电压的变化中消除所选存储元件的电容耦合。

    Developing assembly featuring a developer-carrying member having specified ranges of deformation and hardness and a developer quality control blade having a rough contact surface
    19.
    发明授权
    Developing assembly featuring a developer-carrying member having specified ranges of deformation and hardness and a developer quality control blade having a rough contact surface 失效
    显影组件具有具有特定变形和硬度范围的显影剂承载构件和具有粗糙接触表面的显影剂质量控制刮板

    公开(公告)号:US07016633B2

    公开(公告)日:2006-03-21

    申请号:US11031068

    申请日:2005-01-10

    申请人: Toru Ishigaki

    发明人: Toru Ishigaki

    IPC分类号: G03G15/08

    CPC分类号: G03G15/0812

    摘要: In a developing assembly comprising a developer-carrying member and a developer quantity control blade kept in pressure contact with the developer-carrying member, the developer-carrying member has a deformation percentage D of 0.5% or less in the direction of pressure contact, and the developer quantity control blade has a ten-point average roughness Rz of from 0.3 μm to 20 μm at its surface on the side kept in contact with the developer-carrying member (a charge control face). The developing assembly can prevent faulty images such as lines and uneven images due to the deformation of developer-carrying member even though any deformation due to the pressure contact of the developer quantity control blade has taken place in the developer-carrying member while the developing assembly is stopped.

    摘要翻译: 在显影剂组件中,显影剂承载元件与显影剂承载元件保持压力接触的显影剂承载元件和显影剂量控制刮刀,显影剂承载元件在压接方向上的变形百分数D为0.5%或更小, 显影剂量控制刮板在与显影剂承载构件(充电控制面)保持接触的一侧的表面上的十点平均粗糙度Rz为0.3μm至20μm。 显影组件可以防止由于显影剂承载构件的变形而引起的显影剂承载构件的变形导致的错误图像,例如线和不均匀的图像,即使显影组件中显影剂承载构件发生由于显影剂量控制刮板的压力接触而导致的任何变形 被停止