公开(公告)号：US20160322328A1

公开(公告)日：2016-11-03

申请号：US15205346

申请日：2016-07-08

申请人： ZIPTRONIX, INC.

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20150303263A1

公开(公告)日：2015-10-22

申请号：US14754111

申请日：2015-06-29

申请人： Ziptronix, Inc.

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC分类号： H01L29/16 ,  H01L27/085 ,  H01L29/06

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20140097488A1

公开(公告)日：2014-04-10

申请号：US13646790

申请日：2012-10-08

申请人： Infineon Technologies AG

发明人： Hans-Joachim Schulze ,  Peter Irsigler

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/322

CPC分类号： H01L29/7813 ,  H01L21/223 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3221 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/167 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  Y10S438/974

摘要： A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*1014 cm−3, and partially out-diffusing nitrogen to reduce the nitrogen concentration at least close to the main surface. Further, a semiconductor device is provided.

摘要翻译： 提供一种半导体器件的制造方法。 该方法包括提供包括主表面和布置在主表面上并且具有至少约3×10 14 cm -3的氮浓度的硅层的晶片，并且部分地扩散氮以将氮浓度降低至少接近 主表面。 此外，提供了一种半导体器件。

公开(公告)号：US07867877B2

公开(公告)日：2011-01-11

申请号：US10587725

申请日：2005-01-28

申请人： Etsuro Morita ,  Akihiko Endo

发明人： Etsuro Morita ,  Akihiko Endo

IPC分类号： H01L21/30

CPC分类号： H01L21/76256 ,  H01L21/26533 ,  Y10S438/974

摘要： A method for manufacturing SOI wafers is provided which allows the obtaining of a thin SOI layer having uniform in-plane thickness. In this manufacturing method, an oxygen ion implanted layer is first formed on an active layer wafer. This is then laminated to a base wafer with a embedded oxide film interposed therebetween. The active layer wafer side of the laminated wafer is then ground to remove a portion thereof. The remaining surface side of the active layer wafer is removed by polishing or KOH etching to expose the oxygen ion implanted layer. Oxygen ions are implanted to a uniform depth within the plane of the oxygen ion implanted layer in this oxygen ion implanted layer. Subsequently, oxidizing treatment is carried out to form an oxide film on the exposed surface of the oxygen ion implanted layer. Moreover, this oxide film is removed together with the oxygen ion implanted layer by an HF solution. The remaining portion of the active layer wafer serves as a thin SOI layer.

摘要翻译： 提供一种用于制造SOI晶片的方法，其允许获得具有均匀的面内厚度的薄SOI层。 在该制造方法中，首先在有源层晶片上形成氧离子注入层。 然后将其层压到其间插入有氧化膜的基底晶片。 然后将层压晶片的有源层晶片侧研磨以除去其一部分。 通过抛光或KOH蚀刻去除有源层晶片的剩余表面侧以暴露氧离子注入层。 在该氧离子注入层中，将氧离子注入到氧离子注入层的平面内的均匀深度。 随后，进行氧化处理以在氧离子注入层的暴露表面上形成氧化膜。 此外，通过HF溶液与氧离子注入层一起除去该氧化膜。 有源层晶片的剩余部分用作薄的SOI层。

公开(公告)号：US07700381B2

公开(公告)日：2010-04-20

申请号：US11350027

申请日：2006-02-09

申请人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

发明人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/974 ,  H01L2924/00

摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

摘要翻译： 半导体晶片具有沿其周边形成的斜面轮廓，形成在晶片上的产品和形成在斜面轮廓上的ID标记。 ID标记至少显示产品的性能，制造条件和测试结果。

公开(公告)号：US20090181477A1

公开(公告)日：2009-07-16

申请号：US12410428

申请日：2009-03-24

申请人： Tsu-Jae King ,  Victor Moroz

发明人： Tsu-Jae King ,  Victor Moroz

IPC分类号： H01L21/66

CPC分类号： H01L29/34 ,  H01L21/78 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L2223/5446 ,  Y10S438/974

摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

摘要翻译： 通过在具有预先存在的半导体材料的脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地实现高性能的低功率晶体管， 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术，例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用，以进一步提高器件性能。

公开(公告)号：US07531437B2

公开(公告)日：2009-05-12

申请号：US11360269

申请日：2006-02-22

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/3205

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US07528465B2

公开(公告)日：2009-05-05

申请号：US11673536

申请日：2007-02-09

申请人： Tsu-Jae King ,  Victor Moroz

发明人： Tsu-Jae King ,  Victor Moroz

IPC分类号： H01L29/06

CPC分类号： H01L29/34 ,  H01L21/78 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L2223/5446 ,  Y10S438/974

摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

摘要翻译： 通过在具有预先存在的半导体材料的脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地实现高性能的低功率晶体管， 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术，例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用，以进一步提高器件性能。

公开(公告)号：US20080290470A1

公开(公告)日：2008-11-27

申请号：US12178495

申请日：2008-07-23

申请人： Tsu-Jae King ,  Victor Moroz

发明人： Tsu-Jae King ,  Victor Moroz

IPC分类号： H01L29/06

CPC分类号： H01L29/34 ,  H01L21/78 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L2223/5446 ,  Y10S438/974

摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

摘要翻译： 通过在具有预先存在的半导体材料的脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地实现高性能的低功率晶体管， 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术，例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用，以进一步提高器件性能。

公开(公告)号：US20080063878A1

公开(公告)日：2008-03-13

申请号：US11980415

申请日：2007-10-31

申请人： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

发明人： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

IPC分类号： H01L21/20 ,  B32B9/04

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.