公开(公告)号：US08472255B2

公开(公告)日：2013-06-25

申请号：US13605714

申请日：2012-09-06

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US08369149B2

公开(公告)日：2013-02-05

申请号：US12894889

申请日：2010-09-30

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.

摘要翻译： 在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。 在随后的程序验证迭代中，锁定的存储元件进行全通道升压。 或者，在锁定之后，可以通过多次程序验证迭代来加强升压。 可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。 对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

公开(公告)号：US20110260235A1

公开(公告)日：2011-10-27

申请号：US12887328

申请日：2010-09-21

申请人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

发明人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28291 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/788

摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

摘要翻译： 公开了非电压存储和用于制造非易失性存储器的技术。 在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。 在一个实施例中，控制栅极的下部是p型多晶硅。 控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。 因此，如果控制门耗尽，可能会发生的一些问题得到缓解。 例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

公开(公告)号：US07971127B2

公开(公告)日：2011-06-28

申请号：US11694951

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： G11C11/5642 ,  G06F11/1072 ,  G11C29/00

摘要： Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以使用基于数据中的误差水平的可调节温度参数进行模拟退火。 模拟退火可以将随机性作为噪声引入到解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性增加了灵活性，允许在数据可能不可纠正的情况下可能更快的收敛时间和收敛。

公开(公告)号：US07915124B2

公开(公告)日：2011-03-29

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

公开(公告)号：US20100034022A1

公开(公告)日：2010-02-11

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻的存储元件。

公开(公告)号：US20100006915A1

公开(公告)日：2010-01-14

申请号：US12170327

申请日：2008-07-09

申请人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

发明人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/1203

摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

公开(公告)号：US20090282186A1

公开(公告)日：2009-11-12

申请号：US12338850

申请日：2008-12-18

申请人： Nima Mokhlesi ,  Henry Chin

发明人： Nima Mokhlesi ,  Henry Chin

IPC分类号： G06F12/00

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C29/00

摘要： A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

摘要翻译： 周期性地或响应于错误执行过程，以便基于存储器单元阈值电压分布来动态地和自适应地优化读取比较电平。 该过程的一个实施例包括确定一组非易失性存储元件的阈值电压分布数据，使用加权函数平滑阈值电压分布数据，以创建临时数据集，确定中间数据集的导数，以及 识别和存储导数的正零交叉的负值作为读取的比较点。

公开(公告)号：US20080244368A1

公开(公告)日：2008-10-02

申请号：US11694951

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： G06F11/07 ,  G06F12/00

CPC分类号： G11C11/5642 ,  G06F11/1072 ,  G11C29/00

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以执行使用基于从系统读取的数据中的误差水平的可调节温度参数的模拟退火以辅助迭代解码过程。 模拟退火可以将随机性作为噪声引入到基于度量的解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性在迭代解码期间增加了灵活性，这允许在数据可能不可校正的情况下可能更快的收敛时间和收敛。

公开(公告)号：US20080244367A1

公开(公告)日：2008-10-02

申请号：US11694950

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： G06F11/07 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7209 ,  H03M13/1102

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以执行使用基于从系统读取的数据中的误差水平的可调节温度参数的模拟退火以辅助迭代解码过程。 模拟退火可以将随机性作为噪声引入到基于度量的解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性在迭代解码期间增加了灵活性，这允许在数据可能不可校正的情况下可能更快的收敛时间和收敛。