公开(公告)号：US08559234B2

公开(公告)日：2013-10-15

申请号：US13343972

申请日：2012-01-05

申请人： Noriyasu Kumazaki ,  Susumu Fujimura

发明人： Noriyasu Kumazaki ,  Susumu Fujimura

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage. The second detecting circuit outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage. In a write operation, the switching circuit outputs the second detection signal output from the second detecting circuit. In an operation other than the write operation, the switching circuit outputs the first detection signal output from the first detecting circuit. The recovery control circuit terminates the write operation according to the second detection signal output from the switching circuit.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，第一检测电路，第二检测电路，开关电路和恢复控制电路。 第一检测电路输出第一检测信号，其显示外部供应的外部电源是否等于或大于第一电压。 第二检测电路以比第一检测电路更高的速度输出显示外部电源是否等于或大于第一电压的第二检测信号。 在写入操作中，开关电路输出从第二检测电路输出的第二检测信号。 在写入操作以外的操作中，开关电路输出从第一检测电路输出的第一检测信号。 恢复控制电路根据从开关电路输出的第二检测信号来终止写入操作。

公开(公告)号：US08400838B2

公开(公告)日：2013-03-19

申请号：US13053476

申请日：2011-03-22

申请人： Noriyasu Kumazaki ,  Masafumi Uemura

发明人： Noriyasu Kumazaki ,  Masafumi Uemura

IPC分类号： G11C16/06

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A boosting circuit includes a clock control circuit which outputs a first reference clock signal by controlling the clock signal, and which outputs a second reference clock signal having a same period as that of the first reference clock signal, the second reference clock signal shifted in phase from the first reference clock signal. The boosting circuit includes a first pump clock generation circuit which outputs the first reference clock signal which is input thereto, as a first pump clock signal in accordance with a first pump flag signal. The boosting circuit includes a second pump clock generation circuit which outputs the second reference clock signal which is input thereto, as a second pump clock signal in accordance with a second pump flag signal. The boosting circuit includes a first charge pump which boosts an input voltage in accordance with the first pump clock signal. The boosting circuit includes a second charge pump which boosts an input voltage in accordance with the second pump clock signal.

摘要翻译： 升压电路包括：时钟控制电路，其通过控制时钟信号输出第一参考时钟信号，并输出与第一参考时钟信号具有相同周期的第二参考时钟信号，第二参考时钟信号相移 从第一个参考时钟信号。 升压电路包括：第一泵时钟产生电路，其根据第一泵标志信号输出输入到其的第一参考时钟信号作为第一泵时钟信号。 升压电路包括第二泵时钟产生电路，其根据第二泵标志信号输出输入到其的第二参考时钟信号作为第二泵时钟信号。 升压电路包括第一电荷泵，其根据第一泵时钟信号升压输入电压。 升压电路包括第二电荷泵，其根据第二泵时钟信号升压输入电压。

公开(公告)号：US20100214837A1

公开(公告)日：2010-08-26

申请号：US12552563

申请日：2009-09-02

申请人： Mario SAKO ,  Jun Fujimoto ,  Noriyasu Kumazaki ,  Yasuhiko Honda ,  Yoshihiko Kamata

发明人： Mario SAKO ,  Jun Fujimoto ,  Noriyasu Kumazaki ,  Yasuhiko Honda ,  Yoshihiko Kamata

IPC分类号： G11C16/04 ,  G11C11/00

CPC分类号： G11C5/147 ,  G11C16/0483 ,  G11C16/30

摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.

摘要翻译： 非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。 存储单元阵列包括存储单元。 每个位线与相应的一个存储单元的电流路径的一端电连接。 第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高 第一电压。 第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。