公开(公告)号：US20110249508A1

公开(公告)日：2011-10-13

申请号：US13081868

申请日：2011-04-07

申请人： Mario SAKO

发明人： Mario SAKO

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/24 ,  G11C16/26

摘要： According to one embodiment, a semiconductor storage device includes a memory string, a bit line, a sense simplifier, a first MOS, a first charging-circuit, a second-charging circuit, and a controller. The memory string includes memory cells. The bit line is connected to the memory cell. The sense amplifier applies a voltage to the bit line. The first MOS is electrically connected between the sense amplifier and bit line. The first charging circuit has a first current supply capacity and transfers a first current. The second charging-circuit has a second current supply capacity. The controller controls a first timing to switch from the first current to the second current.

摘要翻译： 根据一个实施例，半导体存储装置包括存储器串，位线，感测简化器，第一MOS，第一充电电路，第二充电电路和控制器。 存储器串包括存储器单元。 位线连接到存储单元。 读出放大器向位线施加电压。 第一MOS电连接在读出放大器和位线之间。 第一充电电路具有第一电流供应能力并传送第一电流。 第二充电电路具有第二电流供应能力。 控制器控制从第一电流切换到第二电流的第一定时。

公开(公告)号：US20100085114A1

公开(公告)日：2010-04-08

申请号：US12564359

申请日：2009-09-22

申请人： Mario SAKO ,  Masaaki Kuwagata ,  Gyosho Chin

发明人： Mario SAKO ,  Masaaki Kuwagata ,  Gyosho Chin

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C8/08

摘要： A voltage generation circuit includes a pump circuit, a first unit, a first switch, and a first capacitor. The pump circuit generates a first voltage and outputs the first voltage to a first node. The first unit includes a first resistance unit to output a second voltage at a second node. The first switch connects the second node and an output terminal. A resistance value of a parasitic resistance formed in an interconnection from the second node to the output terminal is smaller than a resistance value of the first resistance unit. The first capacitor includes one of electrodes and the other electrodes. The one of electrodes is connected to an interconnection connecting the second node and the first switch element. The other of the electrodes is grounded. A capacitance of the first capacitor element is larger than a capacitance connected to the output terminal.

摘要翻译： 电压产生电路包括泵电路，第一单元，第一开关和第一电容器。 泵电路产生第一电压并将第一电压输出到第一节点。 第一单元包括用于在第二节点处输出第二电压的第一电阻单元。 第一个开关连接第二个节点和一个输出端子。 在从第二节点到输出端子的互连中形成的寄生电阻的电阻值小于第一电阻单元的电阻值。 第一电容器包括一个电极和另一个电极。 电极中的一个连接到连接第二节点和第一开关元件的互连。 另一个电极接地。 第一电容器元件的电容大于连接到输出端子的电容。

公开(公告)号：US08358545B2

公开(公告)日：2013-01-22

申请号：US13235416

申请日：2011-09-18

申请人： Mario Sako ,  Yoshihiko Kamata

发明人： Mario Sako ,  Yoshihiko Kamata

IPC分类号： G11C7/10 ,  G11C11/34 ,  G11C16/06 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/26 ,  G11C29/789 ,  G11C29/82

摘要： According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line, and a detecting circuit including a detecting unit. The detecting unit includes a first latch circuit which holds failure information in the memory cell arrays, and a second latch circuit which includes a first input terminal connected to the first signal line, a second input terminal connected to the first latch circuit, and a first output terminal connected to a second signal line.

摘要翻译： 根据一个实施例，半导体存储器包括包括多个存储单元的存储单元阵列，保持存储单元的验证结果并包括感测单元的读出放大器电路，每个列块的感测单元共同连接到 第一信号线和包括检测单元的检测电路。 检测单元包括保存存储单元阵列中的故障信息的第一锁存电路和包括连接到第一信号线的第一输入端，连接到第一锁存电路的第二输入端和第一锁存电路的第二锁存电路， 输出端子连接到第二信号线。

公开(公告)号：US08238154B2

公开(公告)日：2012-08-07

申请号：US12552563

申请日：2009-09-02

申请人： Mario Sako ,  Jun Fujimoto ,  Noriyasu Kumazaki ,  Yasuhiko Honda ,  Yoshihiko Kamata

发明人： Mario Sako ,  Jun Fujimoto ,  Noriyasu Kumazaki ,  Yasuhiko Honda ,  Yoshihiko Kamata

IPC分类号： G11C16/04

CPC分类号： G11C5/147 ,  G11C16/0483 ,  G11C16/30

摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.

摘要翻译： 非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。 存储单元阵列包括存储单元。 每个位线与相应的一个存储单元的电流路径的一端电连接。 第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高 第一电压。 第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

公开(公告)号：US08406057B2

公开(公告)日：2013-03-26

申请号：US13081868

申请日：2011-04-07

申请人： Mario Sako

发明人： Mario Sako

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/24 ,  G11C16/26

摘要： According to one embodiment, a semiconductor storage device includes a memory string, a bit line, a sense simplifier, a first MOS, a first charging-circuit, a second-charging circuit, and a controller. The memory string includes memory cells. The bit line is connected to the memory cell. The sense amplifier applies a voltage to the bit line. The first MOS is electrically connected between the sense amplifier and bit line. The first charging circuit has a first current supply capacity and transfers a first current. The second charging-circuit has a second current supply capacity. The controller controls a first timing to switch from the first current to the second current.

摘要翻译： 根据一个实施例，半导体存储装置包括存储器串，位线，感测简化器，第一MOS，第一充电电路，第二充电电路和控制器。 存储器串包括存储器单元。 位线连接到存储单元。 读出放大器向位线施加电压。 第一MOS电连接在读出放大器和位线之间。 第一充电电路具有第一电流供应能力并传送第一电流。 第二充电电路具有第二电流供应能力。 控制器控制从第一电流切换到第二电流的第一定时。

公开(公告)号：US20120113724A1

公开(公告)日：2012-05-10

申请号：US13235416

申请日：2011-09-18

申请人： Mario SAKO ,  Yoshihiko Kamata

发明人： Mario SAKO ,  Yoshihiko Kamata

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/26 ,  G11C29/789 ,  G11C29/82

摘要： According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line, and a detecting circuit including a detecting unit. The detecting unit includes a first latch circuit which holds failure information in the memory cell arrays, and a second latch circuit which includes a first input terminal connected to the first signal line, a second input terminal connected to the first latch circuit, and a first output terminal connected to a second signal line.

摘要翻译： 根据一个实施例，半导体存储器包括包括多个存储单元的存储单元阵列，保持存储单元的验证结果并包括感测单元的读出放大器电路，每个列块的感测单元共同连接到 第一信号线和包括检测单元的检测电路。 检测单元包括保存存储单元阵列中的故障信息的第一锁存电路和包括连接到第一信号线的第一输入端，连接到第一锁存电路的第二输入端和第一锁存电路的第二锁存电路， 输出端子连接到第二信号线。

公开(公告)号：US20100214837A1

公开(公告)日：2010-08-26

申请号：US12552563

申请日：2009-09-02

申请人： Mario SAKO ,  Jun Fujimoto ,  Noriyasu Kumazaki ,  Yasuhiko Honda ,  Yoshihiko Kamata

发明人： Mario SAKO ,  Jun Fujimoto ,  Noriyasu Kumazaki ,  Yasuhiko Honda ,  Yoshihiko Kamata

IPC分类号： G11C16/04 ,  G11C11/00

CPC分类号： G11C5/147 ,  G11C16/0483 ,  G11C16/30

摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.

摘要翻译： 非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。 存储单元阵列包括存储单元。 每个位线与相应的一个存储单元的电流路径的一端电连接。 第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高 第一电压。 第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

公开(公告)号：US08379451B2

公开(公告)日：2013-02-19

申请号：US13235392

申请日：2011-09-18

申请人： Mario Sako ,  Takahiro Suzuki

发明人： Mario Sako ,  Takahiro Suzuki

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C7/10

CPC分类号： G11C29/32 ,  G11C16/0483 ,  G11C16/06 ,  G11C29/50004

摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cells, a logic gate chain, and a counter. The memory cells are capable of retaining data and are associated with the columns. The logic gate chain includes a plurality of logic gates associated with the columns. Each of the logical gates outputs a logical level to a next-stage logical gate in the series connection. The logic level indicates presence or absence of verify-failure in the associated column. The counter counts the number of output times of the logic level indicating the presence of the verify-failure in a final-stage logic gate of the series connection. A content indicated by the logic level output from each of the logic gates is inverted at a boundary of the logic gate associated with the column having the verify-failure in the logic gate chain.

摘要翻译： 根据一个实施例，半导体存储器件包括多个存储单元，逻辑门链和计数器。 存储单元能够保留数据并与列相关联。 逻辑门链包括与列相关联的多个逻辑门。 每个逻辑门将逻辑电平输出到串联连接中的下一级逻辑门。 逻辑电平表示相关列中存在或不存在验证失败。 计数器计数指示在串联连接的最后阶段逻辑门中存在验证失败的逻辑电平的输出次数。 由逻辑门输出的逻辑电平指示的内容在与具有逻辑门链中的验证失败的列相关联的逻辑门的边界处被反转。

公开(公告)号：US20120243320A1

公开(公告)日：2012-09-27

申请号：US13235392

申请日：2011-09-18

申请人： Mario Sako ,  Takahiro Suzuki

发明人： Mario Sako ,  Takahiro Suzuki

IPC分类号： G11C16/04

CPC分类号： G11C29/32 ,  G11C16/0483 ,  G11C16/06 ,  G11C29/50004

摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cells, a logic gate chain, and a counter. The memory cells are capable of retaining data and are associated with the columns. The logic gate chain includes a plurality of logic gates associated with the columns. Each of the logical gates outputs a logical level to a next-stage logical gate in the series connection. The logic level indicates presence or absence of verify-failure in the associated column. The counter counts the number of output times of the logic level indicating the presence of the verify-failure in a final-stage logic gate of the series connection. A content indicated by the logic level output from each of the logic gates is inverted at a boundary of the logic gate associated with the column having the verify-failure in the logic gate chain.

摘要翻译： 根据一个实施例，半导体存储器件包括多个存储单元，逻辑门链和计数器。 存储单元能够保留数据并与列相关联。 逻辑门链包括与列相关联的多个逻辑门。 每个逻辑门将逻辑电平输出到串联连接中的下一级逻辑门。 逻辑电平表示相关列中存在或不存在验证失败。 计数器计数指示在串联连接的最后阶段逻辑门中存在验证失败的逻辑电平的输出次数。 由逻辑门输出的逻辑电平指示的内容在与具有逻辑门链中的验证失败的列相关联的逻辑门的边界处被反转。