Integrated circuit for reception apparatus

    公开(公告)号:US11539378B2

    公开(公告)日:2022-12-27

    申请号:US17322541

    申请日:2021-05-17

    Abstract: Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

    Reception device and reception method

    公开(公告)号:US11515965B2

    公开(公告)日:2022-11-29

    申请号:US17729658

    申请日:2022-04-26

    Abstract: A reception device includes: a receiver that receives a multiplexed signal; a first demapper that demaps the multiplexed signal, with a second modulated symbol stream of a second data series being included in the multiplexed signal as an undefined signal component, to generate a first bit likelihood stream of a first data series; a second demapper that demaps the multiplexed signal, with a first modulated symbol stream of the first data series being included in the multiplexed signal as an undefined signal component, to generate a second bit likelihood stream of the second data series; a first decoder that performs error control decoding on the first bit likelihood stream to derive the first data series; and a second decoder that performs error control decoding on the second bit likelihood stream to derive the second data series.

    Communication apparatus and communication method

    公开(公告)号:US11057084B2

    公开(公告)日:2021-07-06

    申请号:US16551084

    申请日:2019-08-26

    Abstract: Provided are M signal processors that respectively generate modulated signals for M reception apparatuses (where M is an integer equal to 2 or greater), a multiplexing signal processor, and N antenna sections (where N is an integer equal to 1 or greater). When transmitting multiple streams, each of the M signal processors generates two mapped signals, generates first and second precoded signals by precoding the two mapped signals, periodically changes the phase of signal points in the IQ plane with respect to the second precoded signal, outputs the phase-changed signal, and outputs the first precoded signal and the phase-changed second precoded signal as two modulated signals. When transmitting a single stream, each of the M signal processor outputs a single modulated signal. The multiplexing signal processor multiplexes the modulated signals output from the M signal processors, and generates N multiplexed signals. The N antenna sections respectively transmit the N multiplexed signals.

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