公开(公告)号：US12028554B2

公开(公告)日：2024-07-02

申请号：US18052108

申请日：2022-11-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chu Tong Wang ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167 ,  H04N19/17 ,  H04N19/186

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167 ,  H04N19/17 ,  H04N19/186

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US11956434B2

公开(公告)日：2024-04-09

申请号：US18062335

申请日：2022-12-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/169 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/1887

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

公开(公告)号：US11936893B2

公开(公告)日：2024-03-19

申请号：US17526098

申请日：2021-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/46 ,  H04N19/184 ,  H04N19/65

CPC classification number: H04N19/46 ,  H04N19/184 ,  H04N19/65

Abstract: An encoder that includes memory and circuitry coupled to the memory. The circuitry encodes a slice into one or more data access regions in a variable length encoding process. The circuitry encodes one or more offsets into a slice header, based on a flag written into a sequence header and a total number of the one or more data access regions. The one or more offsets each specify a head position of a corresponding one of the one or more data access regions in a bitstream. When the flag indicates that the one or more offsets are to be encoded and the total number is at least two, the one or more offsets are encoded. The flag switches between encoding and not encoding the one or more offsets regardless of whether the total number is at least two.

公开(公告)号：US11871028B2

公开(公告)日：2024-01-09

申请号：US17376682

申请日：2021-07-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/52 ,  H04N19/109 ,  H04N19/139 ,  H04N19/176 ,  H04N19/577

CPC classification number: H04N19/52 ,  H04N19/109 ,  H04N19/139 ,  H04N19/176 ,  H04N19/577

Abstract: An encoder: generates, in an inter prediction mode, a first prediction image of a current block to be processed, based on a derived motion vector; and generates a final prediction image of the current block by applying an update process to the first prediction image. Candidates for the update process include a first process and a second process. The first process is a BDOF process. The second process is a process of mixing the first prediction image with a second prediction image generated in intra prediction for the current block. In the applying of the update process, the first process and the second process are mutually exclusively applied.

公开(公告)号：US11750842B2

公开(公告)日：2023-09-05

申请号：US17724298

申请日：2022-04-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Che Wei Kuo ,  Chong Soon Lim ,  Chu Tong Wang ,  Han Boon Teo ,  Hai Wei Sun ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

CPC classification number: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US11503281B2

公开(公告)日：2022-11-15

申请号：US17681051

申请日：2022-02-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Che Wei Kuo ,  Hai Wei Sun ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.

公开(公告)号：US11115671B2

公开(公告)日：2021-09-07

申请号：US17025629

申请日：2020-09-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei Kuo ,  Chong Soon Lim ,  Han Boon Teo ,  Jing Ya Li ,  Hai Wei Sun ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/00 ,  H04N19/44 ,  H04N19/105 ,  H04N19/117 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/46

Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.

公开(公告)号：US12294707B2

公开(公告)日：2025-05-06

申请号：US18587635

申请日：2024-02-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/169 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

公开(公告)号：US12294696B2

公开(公告)日：2025-05-06

申请号：US18529380

申请日：2023-12-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Che Wei Kuo ,  Hai Wei Sun ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.

公开(公告)号：US12289462B2

公开(公告)日：2025-04-29

申请号：US17642448

申请日：2020-12-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Han Boon Teo ,  Hai Wei Sun ,  Jing Ya Li ,  Che Wei Kuo ,  Chong Soon Lim ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/00 ,  H04N19/105 ,  H04N19/176 ,  H04N19/46 ,  H04N19/80

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry writes, into a bitstream, a first flag indicating whether or not to enable a first process of applying a filter to a first image to generate a second image, holding the second image as a reference image, and displaying the second image. When the first process is not enabled, circuitry writes, into the bitstream, one or more parameters for controlling a second process of applying the filter to the first image to generate the second image, holding the first image as a reference image, and displaying the second image.