公开(公告)号：US20100169846A1

公开(公告)日：2010-07-01

申请号：US12717885

申请日：2010-03-04

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5063 ,  G06F17/5081 ,  G06F2217/78 ,  H01L27/0207 ,  H01L27/11807

摘要： Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

摘要翻译： 公开了用于产生用于制造集成电路的偏置布局的方法。 一种这样的方法包括获得由一个或多个单元限定的标称布局，其中每个单元具有具有标称栅极长度的一个或多个晶体管栅极特征。 然后，获取注释的布局。 注释布局包含描述标称布局的一个或多个单元中的一个或多个晶体管栅极特征的栅极长度偏置的信息。 通过使用来自注释布局的信息修改标称布局来产生偏置布局。 偏置修改由注释布局的信息识别的那些晶体管栅极特征的栅极长度。

公开(公告)号：US07745239B1

公开(公告)日：2010-06-29

申请号：US11486511

申请日：2006-07-14

申请人： O. Samuel Nakagawa ,  Andrew B. Kahng ,  Pakman Wong ,  Puneet Gupta

发明人： O. Samuel Nakagawa ,  Andrew B. Kahng ,  Pakman Wong ,  Puneet Gupta

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/44

CPC分类号： H01L21/7684 ,  G06F17/5068 ,  G06F17/5081 ,  H01L21/76819 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a “keep out” distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the “keep out” distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.

摘要翻译： 具有金属互连层的集成电路，并且还具有限定了与导线之间的距离相等的距离的导电线和边界，该边界界定了边界与导电线之间的“保持距离”。 一组第一填充元件沿着“保留”距离外的边界被均匀地布置，并且距离导电线比第一填充元件更远的一组第二填充元件以均匀的图案布置，但是对于 在模式中缺少一些填充元素。

公开(公告)号：US07627849B1

公开(公告)日：2009-12-01

申请号：US11386268

申请日：2006-03-21

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method for improving a resolution enhanced (RE) layout produced by an RE program that starts with a nominal integrated circuit layout. For at least one feature of said layout at least one critical feature quality is chosen from a set of feature qualities and at least one starting condition of said resolution enhancement program is adjusted in response to said at least one critical feature quality.

摘要翻译： 一种用于改善以标称集成电路布局开始的RE程序产生的分辨率增强（RE）布局的方法。 对于所述布局的至少一个特征，从一组特征质量中选择至少一个关键特征质量，并且响应于所述至少一个关键特征质量来调整所述分辨率增强程序的至少一个起始条件。

公开(公告)号：US08127266B1

公开(公告)日：2012-02-28

申请号：US12212353

申请日：2008-09-17

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50 ,  G06F15/04

CPC分类号： G06F17/5068 ,  G06F17/5063 ,  G06F17/5081 ,  G06F2217/78 ,  H01L27/0207 ,  H01L27/11807

摘要： Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

摘要翻译： 描述了用于优化集成数字电路的栅极长度偏置方法的方法和装置。 栅极长度偏置方法用偏置栅极长度替代晶体管的标称栅极长度，其中偏置栅极长度包括与标称栅极长度相比较小的偏置长度。 在示例性实施例中，偏置长度小于额定栅极长度的10％。

公开(公告)号：US20100169847A1

公开(公告)日：2010-07-01

申请号：US12717887

申请日：2010-03-04

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

摘要翻译： 公开了一种标准细胞库。 标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。 栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。 标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。 注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

公开(公告)号：US07614032B2

公开(公告)日：2009-11-03

申请号：US11637209

申请日：2006-12-11

申请人： Andrew B. Kahng ,  Puneet Gupta ,  Dennis Sylvester ,  Jie Yang

发明人： Andrew B. Kahng ,  Puneet Gupta ,  Dennis Sylvester ,  Jie Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.

摘要翻译： 用于执行掩模设计布局分辨率增强的方法包括以最小的总校正成本为预定参数产量确定设计布局的校正级别。 如果需要校正，则基于校正算法在确定的校正水平校正设计布局。 以这种方式，仅修改设计布局上对于获得期望的性能收益至关重要的印刷特征，从而降低了校正设计布局的总成本。

公开(公告)号：US07149999B2

公开(公告)日：2006-12-12

申请号：US10787070

申请日：2004-02-25

申请人： Andrew B. Kahng ,  Puneet Gupta ,  Dennis Sylvester ,  Jie Yang

发明人： Andrew B. Kahng ,  Puneet Gupta ,  Dennis Sylvester ,  Jie Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for performing a mask design layout resolution enhancement includes determining a level of correction for a mask design layout for a predetermined parametric yield with a minimum total correction cost. The mask design layout is corrected at a determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the mask design layout that are critical for obtaining a desired performance yield are corrected, thereby reducing total cost of correction of the mask design layout.

摘要翻译： 用于执行掩模设计布局分辨率增强的方法包括以最小的总校正成本确定用于预定参数产量的掩模设计布局的校正级别。 如果需要校正，则基于校正算法在确定的校正水平校正掩模设计布局。 以这种方式，仅修正了掩模设计布局上对于获得期望的性能产出至关重要的打印特征，从而降低了掩模设计布局校正的总成本。

公开(公告)号：US08869094B2

公开(公告)日：2014-10-21

申请号：US13620683

申请日：2012-09-14

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

公开(公告)号：US20130014072A1

公开(公告)日：2013-01-10

申请号：US13620683

申请日：2012-09-14

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

公开(公告)号：US08185865B2

公开(公告)日：2012-05-22

申请号：US12717885

申请日：2010-03-04

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50 ,  G06F15/04

CPC分类号： G06F17/5068 ,  G06F17/5063 ,  G06F17/5081 ,  G06F2217/78 ,  H01L27/0207 ,  H01L27/11807

摘要： Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

摘要翻译： 公开了用于产生用于制造集成电路的偏置布局的方法。 一种这样的方法包括获得由一个或多个单元限定的标称布局，其中每个单元具有具有标称栅极长度的一个或多个晶体管栅极特征。 然后，获取注释的布局。 注释布局包含描述标称布局的一个或多个单元中的一个或多个晶体管栅极特征的栅极长度偏置的信息。 通过使用来自注释布局的信息修改标称布局来产生偏置布局。 偏置修改由注释布局的信息识别的那些晶体管栅极特征的栅极长度。