公开(公告)号：US20140361830A1

公开(公告)日：2014-12-11

申请号：US13911902

申请日：2013-06-06

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Yunfei Shi

IPC: H03F1/02

CPC classification number: H03F1/02 ,  H03F1/0222 ,  H03F1/0227 ,  H03F3/195 ,  H03F2200/102 ,  H03F2200/432 ,  H03F2200/435 ,  H03F2200/504

Abstract: Techniques for efficiently generating a variable boosted supply voltage for an amplifier and/or other circuits are disclosed. In an exemplary design, an apparatus includes an amplifier, a boost converter, and a boost controller. The amplifier receives an envelope signal and a variable boosted supply voltage and provides an output voltage and an output current. The boost converter receives a power supply voltage and at least one signal determined based on the envelope signal and generates the variable boosted supply voltage based on the power supply voltage and the at least one signal. The boost controller generates the at least one signal (e.g., an enable signal and/or a threshold voltage) for the boost converter based on the envelope signal and/or the output voltage. The boost converter is enabled or disabled based on the enable signal and generates the variable boosted supply voltage based on the power supply voltage and the threshold voltage.

Abstract translation: 公开了用于有效地产生放大器和/或其他电路的可变提升电源电压的技术。 在示例性设计中，装置包括放大器，升压转换器和升压控制器。 放大器接收包络信号和可变提升电源电压，并提供输出电压和输出电流。 升压转换器接收基于包络信号确定的电源电压和至少一个信号，并且基于电源电压和至少一个信号产生可变升压的电源电压。 升压控制器基于包络信号和/或输出电压产生用于升压转换器的至少一个信号（例如，使能信号和/或阈值电压）。 升压转换器基于使能信号使能或禁止，并根据电源电压和阈值电压产生可变升压电源电压。

公开(公告)号：US11929766B2

公开(公告)日：2024-03-12

申请号：US17659468

申请日：2022-04-15

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Brian Clarke Banister ,  Christos Komninakis ,  Minkui Liu

IPC: H04B1/26 ,  H04B1/00 ,  H04B1/403 ,  H04B1/58

CPC classification number: H04B1/0007 ,  H04B1/0053 ,  H04B1/403 ,  H04B1/588

Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.

公开(公告)号：US10039526B2

公开(公告)日：2018-08-07

申请号：US14857575

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Sameer Wadhwa ,  Lennart Karl-Axel Mathe

IPC: A61B8/00 ,  A61B8/08 ,  A61B8/14 ,  G06K9/00

Abstract: Apparatus and method for generating a DC pixel voltage are disclosed. The apparatus includes an amplifier configured to amplify an input signal to generate a voltage signal, wherein the input signal is generated in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating via a piezoelectric layer; a noise reduction circuit configured to pass the voltage signal from an output of the amplifier to a node, while reducing a propagation of noise from the output of the amplifier to the node; and a circuit configured to generate a DC pixel voltage based on the reduced-noise voltage signal.

公开(公告)号：US10004432B2

公开(公告)日：2018-06-26

申请号：US14842826

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Sameer Wadhwa ,  Lingli Xia

IPC: H03K17/00 ,  A61B5/117 ,  G01S15/89 ,  G06K9/00 ,  G01S7/52 ,  H03K17/975 ,  H01L27/20

CPC classification number: A61B5/117 ,  G01S7/52079 ,  G01S15/8906 ,  G06K9/0002 ,  H01L27/20 ,  H03K17/975

Abstract: An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.

公开(公告)号：US09882479B2

公开(公告)日：2018-01-30

申请号：US14857080

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M3/1584

Abstract: In one embodiment, a switching regulator includes a first switching regulator stage configured between an input voltage and a first reference voltage and a second switching regulator stage configured between the first reference voltage and a second reference voltage. A first terminal of an inductor is coupled to an output of the first switching regulator stage and an output of the second switching regulator stage. The first switching regulator stage operates to produce an output voltage when the output voltage is configured above the first reference voltage, and the second switching regulator stage operates to produce an output voltage when the output voltage is configured below the first reference voltage.

公开(公告)号：US20170059699A1

公开(公告)日：2017-03-02

申请号：US14842826

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Sameer Wadhwa ,  Lingli Xia

IPC: G01S7/52 ,  A61B5/117

CPC classification number: A61B5/117 ,  G01S7/52079 ,  G01S15/8906 ,  G06K9/0002 ,  H01L27/20 ,  H03K17/975

Abstract: An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.

Abstract translation: 公开了一种诸如用于超声波成像装置的像素传感器的装置。 该装置包括耦合到压电层的第一金属化层，其中在第一金属化层处响应于反射待被成像的物体（例如，用户的指纹）并传播通过的超声波形成第一电压 所述压电层，并且其中所述第一金属化层位于衬底上方; 位于第一金属化层和衬底之间的第二金属化层; 以及被配置为向第二金属化层施加第二电压以减小第一金属化层和衬底之间的寄生电容的器件。

公开(公告)号：US09372492B2

公开(公告)日：2016-06-21

申请号：US13740062

申请日：2013-01-11

Applicant: QUALCOMM Incorporated

Inventor： Song S Shi ,  Pengfei Li ,  Lennart Karl-Axel Mathe ,  Yunfei Shi

IPC: H02M3/156 ,  G05F3/02 ,  H03F1/02 ,  H02M3/155 ,  H02M3/158

CPC classification number: G05F3/02 ,  H02M3/155 ,  H02M3/1582 ,  H02M2001/008 ,  H03F1/0238

Abstract: Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst/T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking/delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks.

Abstract translation: 用于从降压转换器时钟信号产生用于升压转换器的升压时钟信号的技术，其中所述升压时钟信号具有有限的频率范围。 在一方面，升压时钟信号具有由Vbst / T确定的最大频率，其中Vbst表示目标输出电压和电池电压之间的差，T表示预定的周期持续时间。 升压转换器可以包括用于限制升压时钟信号的最小频率的脉冲插入块以及限制升压时钟信号的最大频率的动态消隐/延迟模块。 公开了通常实现最小频率限制和最大频率限制块的其它技术。

公开(公告)号：US08866547B2

公开(公告)日：2014-10-21

申请号：US13752287

申请日：2013-01-28

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Pengfei Li ,  Song S Shi ,  Yunfei Shi ,  Joseph D Rutkowski

IPC: H03F99/00 ,  H03G1/00

CPC classification number: H03F1/0222 ,  H03F1/0227 ,  H03F3/19 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/451

Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.

Abstract translation: 用于动态产生包络跟踪系统的净空电压的技术。 在一方面，当来自功率放大器（PA）的信号指示PA余量不足时，更新初始余量电压。 初始余量电压可以被更新为包括初始电压加上缺陷电压加上余量的操作净空电压。 以这种方式，可以动态选择操作净空电压以最小化功耗，同时仍然确保PA是线性的。 在另一方面，描述了使用计数器的净空电压发生器的具体示例性实施例。

公开(公告)号：US20140210548A1

公开(公告)日：2014-07-31

申请号：US13752282

申请日：2013-01-28

Applicant: QUALCOMM INCORPORATED

Inventor： Song S. Shi ,  Pengfei Li ,  Lennart Karl-Axel Mathe

IPC: G05F1/618 ,  H03G1/00

CPC classification number: H03G1/0005 ,  H02M1/088 ,  H02M3/158 ,  H02M2001/0045 ,  H02M2001/0058 ,  Y02B70/1491

Abstract: Techniques for reducing ringing arising from L-C coupling in a boost converter circuit during a transition from a boost ON state to a boost OFF state. In an aspect, during an OFF state of the boost converter circuit, the size of the high-side switch coupling a boost inductor to the load is gradually increased over time. In this manner, the on-resistance of the high-side switch is decreased from a first value to a second (lower) value over time, which advantageously reduces ringing (due to high quality factor or Q) when initially entering the OFF state, while maintaining low conduction losses during the remainder of the OFF state. Further techniques are provided for implementing the high-side switch as a plurality of parallel-coupled transistors.

Abstract translation: 在升压转换电路从升压导通状态转换到升压关断状态时，减少由升压转换器电路中的L-C耦合引起振铃的技术。 在一方面，在升压转换器电路的OFF状态期间，将升压电感器耦合到负载的高侧开关的尺寸随时间逐渐增加。 以这种方式，高边开关的导通电阻随着时间从第一值降低到第二（较低）值，这有利于当初始进入截止状态时减少振铃（由于高品质因数或Q） 同时在关闭状态的剩余期间保持低导通损耗。 提供了用于将高侧开关实现为多个并联耦合晶体管的进一步技术。

公开(公告)号：US12267075B2

公开(公告)日：2025-04-01

申请号：US18323942

申请日：2023-05-25

Applicant: QUALCOMM Incorporated

Inventor： Sameer Wadhwa ,  Lennart Karl-Axel Mathe

IPC: H03K5/00 ,  H03K5/14 ,  H03K5/1534 ,  H03K5/19 ,  H03K5/15 ,  H03K5/1536

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.