公开(公告)号：US20190179399A1

公开(公告)日：2019-06-13

申请号：US16268634

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F1/3234 ,  G06F13/42 ,  G06F12/06 ,  G11C7/10 ,  G06F13/16 ,  G06F1/3225

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

公开(公告)号：US12159033B2

公开(公告)日：2024-12-03

申请号：US18047493

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Michael Hawjing Lo ,  Subbarao Palacharla ,  Olivier Alavoine

IPC: G06F3/06

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

公开(公告)号：US20240385747A1

公开(公告)日：2024-11-21

申请号：US18320492

申请日：2023-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Michael Hawjing Lo

IPC: G06F3/06

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method includes receiving, from a host, a message comprising instructions to configure a first portion of a memory array for storage of data and metadata and to configure a second portion of the memory array for storage of only data and configuring the memory array in accordance with the received message. Other aspects and features are also claimed and described.

公开(公告)号：US11631450B2

公开(公告)日：2023-04-18

申请号：US17377799

申请日：2021-07-16

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US11372717B2

公开(公告)日：2022-06-28

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

公开(公告)号：US10852809B2

公开(公告)日：2020-12-01

申请号：US16268634

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G06F1/3234 ,  G06F1/3225 ,  G06F13/42

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

公开(公告)号：US20250060877A1

公开(公告)日：2025-02-20

申请号：US18939310

申请日：2024-11-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Sharadchandra Deshmukh ,  Michael Hawjing Lo ,  Subbarao Palacharla ,  Olivier Alavoine

IPC: G06F3/06

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

公开(公告)号：US20240126438A1

公开(公告)日：2024-04-18

申请号：US18047493

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Pankaj Sharadchandra Deshmukh ,  Michael Hawjing Lo ,  Subbarao Palacharla ,  Olivier Alavoine

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

公开(公告)号：US20230359373A1

公开(公告)日：2023-11-09

申请号：US17661810

申请日：2022-05-03

Applicant: QUALCOMM Incorporated

Inventor： Engin Ipek ,  Hamza Omar ,  Bohuslav Rychlik ,  Saumya Ranjan Kuanr ,  Behnam Dashtipour ,  Michael Hawjing Lo ,  Jeffrey Gemar ,  Matthew Severson ,  George Patsilaras ,  Andrew Edmund Turner

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.

公开(公告)号：US11295803B2

公开(公告)日：2022-04-05

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated ,  Candace Sachi Chun

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.