公开(公告)号：US20220206520A1

公开(公告)日：2022-06-30

申请号：US17138463

申请日：2020-12-30

Applicant: QUALCOMM Incorporated

Inventor： Jize JIANG ,  Hua GUAN ,  Kuan Chuang KOAY

IPC: G05F1/56

Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.

公开(公告)号：US20190146531A1

公开(公告)日：2019-05-16

申请号：US15813629

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Chi Fan YUNG ,  Hua GUAN ,  Ngai Yeung HO ,  Kan LI

IPC: G05F1/575 ,  G11C7/06 ,  G05F1/563 ,  G11C11/4074 ,  G11C5/14 ,  G05F3/24 ,  G11C7/10

Abstract: Certain aspects of the present disclosure generally relate a regulator. For example, the regulator may include a control stage, a sense capacitor having first and second terminals, the first terminal coupled to an output of the voltage regulator, and a current amplifier having an input coupled to the second terminal of the sense capacitor and an output coupled to the control stage. The control stage of the regulator may adjust the output voltage of the regulator based at least in part on a current generated by the current amplifier.

公开(公告)号：US20180120879A1

公开(公告)日：2018-05-03

申请号：US15438605

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Mengmeng DU ,  Hua GUAN

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/56

Abstract: A voltage regulation circuit improves power supply rejection ratio and load-transient performance. The voltage regulation circuit includes a low dropout (LDO) voltage regulator and an inverting amplifier stage. The LDO voltage regulator includes a first error amplifier and a power field effect transistor (FET). The first error amplifier includes a first input and a second input. The second input receives an output signal fed back from the LDO voltage regulator. The inverting amplifier stage includes an output terminal coupled to the first input of the first error amplifier. The inverting amplifier stage also includes a first input that receives the output fed back from the LDO voltage regulator and a second input that receives a reference voltage.

公开(公告)号：US20230280773A1

公开(公告)日：2023-09-07

申请号：US18315402

申请日：2023-05-10

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang KOAY ,  Hua GUAN ,  Jize JIANG

IPC: G05F1/56 ,  H03F3/16

CPC classification number: G05F1/56 ,  H03F3/16

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor.

公开(公告)号：US20220342434A1

公开(公告)日：2022-10-27

申请号：US17239377

申请日：2021-04-23

Applicant: QUALCOMM Incorporated

Inventor： Xiaodong MENG ,  Fan YANG ,  YuFei PAN ,  Hua GUAN ,  Kuan Chuang KOAY ,  Jize JIANG

IPC: G05F1/59 ,  G05F1/575 ,  H04B1/40

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

公开(公告)号：US20220308609A1

公开(公告)日：2022-09-29

申请号：US17213044

申请日：2021-03-25

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang KOAY ,  Hua GUAN ,  Jize JIANG

IPC: G05F1/56 ,  H03F3/16

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.

公开(公告)号：US20180107232A1

公开(公告)日：2018-04-19

申请号：US15296608

申请日：2016-10-18

Applicant: QUALCOMM Incorporated

Inventor： Chi Fan YUNG ,  Xiaodan ZOU ,  Ngai Yeung HO ,  Kan LI ,  Hua GUAN

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: Certain aspects of the present disclosure generally relate a dual feedback loop regulator. For example, the regulator may include a first amplifier having an output coupled to an output node of the regulator, the output node further coupled to a first feedback path and a second feedback path of the regulator. A first input of a second amplifier may be coupled to the first feedback path and a second input of the second amplifier may be coupled to a reference path. The regulator may also include a transconductance stage having a first transistor and a first current source, the first transistor and the current source coupled to the first feedback path and the second feedback path, and a transimpedance stage coupled to the transconductance stage and an input of the first amplifier.