公开(公告)号：US09831272B2

公开(公告)日：2017-11-28

申请号：US15264560

申请日：2016-09-13

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Satyanarayana Sahu ,  Hyeokjin Lim ,  Mukul Gupta

IPC: H01L27/118 ,  H01L29/06

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0649 ,  H01L2027/11829 ,  H01L2027/11866

Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

公开(公告)号：US20220102266A1

公开(公告)日：2022-03-31

申请号：US17038098

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Stanley Seungchul Song ,  Foua Vang ,  Seung Hyuk Kang

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

公开(公告)号：US11133803B2

公开(公告)日：2021-09-28

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US10692808B2

公开(公告)日：2020-06-23

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

公开(公告)号：US20190237542A1

公开(公告)日：2019-08-01

申请号：US15886611

申请日：2018-02-01

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

IPC: H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L29/0696 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0642 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2027/11831 ,  H01L2027/11875

Abstract: According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

公开(公告)号：US10236886B2

公开(公告)日：2019-03-19

申请号：US15393180

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim ,  Mickael Malabry ,  Mukul Gupta

IPC: H01L23/528 ,  H03K19/0948 ,  H01L27/118 ,  H01L23/522 ,  H01L27/02 ,  H01L27/092

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.