公开(公告)号：US20230352423A1

公开(公告)日：2023-11-02

申请号：US17661029

申请日：2022-04-27

Applicant: QUALCOMM Incorporated

Inventor： Sameer Sunil VADHAVKAR ,  Changhan Hobie YUN ,  Paragkumar Ajaybhai THADESAR ,  Nosun PARK ,  Daniel Daeik KIM

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/304

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L21/304

Abstract: Disclosed is a device that includes a die and a protection layer surrounding the die. The protection layer is applied at a backend process prior to dicing a wafer to individual dies. The protection layer protects the die from chips and cracks during and after dicing the wafer.

公开(公告)号：US20230223362A1

公开(公告)日：2023-07-13

申请号：US17575492

申请日：2022-01-13

Applicant: QUALCOMM Incorporated

Inventor： FNU SURAJ PRAKASH ,  Paragkumar Ajaybhai THADESAR ,  John Jong-Hoon LEE ,  Nikhil RAMAN ,  Peng SONG ,  Francesco CARRARA

IPC: H01L23/64 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/528 ,  H01L28/10

Abstract: A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor through the second inductor.

公开(公告)号：US20230187340A1

公开(公告)日：2023-06-15

申请号：US17547093

申请日：2021-12-09

Applicant: QUALCOMM Incorporated

Inventor： Nosun PARK ,  Changhan Hobie YUN ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L28/40 ,  H01L28/10

Abstract: An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.

公开(公告)号：US20220069453A1

公开(公告)日：2022-03-03

申请号：US17002594

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Nosun PARK ,  Sameer Sunil VADHAVKAR

IPC: H01Q1/38 ,  H04B3/52 ,  H04B3/56 ,  H01Q13/02 ,  H01Q21/28

Abstract: A substrate that includes at least one dielectric layer, a plurality of interconnects, and a curved antenna coupled to a surface of the substrate. The curved antenna is curved relative to the surface of the substrate such that at least part of the curved antenna is offset from the surface of the substrate. The substrate includes a first antenna dielectric layer coupled to the surface of the substrate, an antenna ground interconnect coupled to the first antenna dielectric layer, and a second antenna dielectric layer coupled to the antenna ground interconnect. The antenna ground interconnect configured to be coupled to ground. The curved antenna is coupled to the second antenna dielectric layer.