公开(公告)号：US20220069193A1

公开(公告)日：2022-03-03

申请号：US17005168

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Nosun PARK ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR

IPC: H01L41/08 ,  H03H9/02

Abstract: A package that includes an integrated device, an integrated passive device and a void. The integrated device is configured as a filter. The integrated device includes a substrate comprising a piezoelectric material, and at least one metal layer coupled to a first surface of the first substrate. The integrated passive device is coupled to the integrated device. The integrated passive device is configured as a cap for the integrated device. The void is located between the integrated device and the integrated passive device.

公开(公告)号：US20230230910A1

公开(公告)日：2023-07-20

申请号：US17579038

申请日：2022-01-19

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Nosun PARK ,  Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/49816 ,  H01L24/14 ,  H01L2924/15311

Abstract: A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

公开(公告)号：US20170338179A1

公开(公告)日：2017-11-23

申请号：US15161126

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Paragkumar Ajaybhai THADESAR ,  Young Kyu SONG ,  John Jong-Hoon LEE ,  Sangjo CHOI

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/85 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L24/09 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2224/45099

Abstract: Low inductance to ground can be provided in wire-bond based device packages. An example device package may include a die on a package substrate, a mold on the package substrate and encapsulating the die, an upper ground conductor on the mold, and ground wire bonds within the mold. The die may include a plurality of terminals on an upper surface of the die. The plurality of ground wire bonds may electrically couple the die and the upper ground conductor. For each ground wire bond, a first end of that ground wire bond may be configured to electrically couple to a corresponding terminal on the upper surface of the die and a second end of that ground wire bond may be configured to electrically couple to the upper ground conductor at the upper surface of the mold.

公开(公告)号：US20220223516A1

公开(公告)日：2022-07-14

申请号：US17149006

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Nosun PARK ,  Changhan Hobie YUN ,  Daniel Daeik KIM ,  Sameer Sunil VADHAVKAR ,  Paragkumar Ajaybhai THADESAR

IPC: H01L23/522 ,  H01L27/01 ,  H01L21/70

Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.

公开(公告)号：US20210351750A1

公开(公告)日：2021-11-11

申请号：US16870383

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik KIM ,  Paragkumar Ajaybhai THADESAR ,  Changhan Hobie YUN ,  Sameer Sunil VADHAVKAR ,  Nosun PARK

IPC: H03F3/213 ,  H03F3/195 ,  H03F1/56 ,  H01L23/66 ,  H01L23/34

Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.

公开(公告)号：US20200020473A1

公开(公告)日：2020-01-16

申请号：US16035378

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU ,  Paragkumar Ajaybhai THADESAR ,  Jonghae KIM

IPC: H01F17/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/02

Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

公开(公告)号：US20240297165A1

公开(公告)日：2024-09-05

申请号：US18177404

申请日：2023-03-02

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR ,  Youngju PARK ,  Doosoub SHIN

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/50 ,  H01L27/01 ,  H01L23/49811 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92125

Abstract: A device is described, including a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate, through at least a first pair of conductive pillars. The device also includes a laminate substrate coupled to the first surface of the RDL substrate through at least a second pair of conductive pillars.

公开(公告)号：US20220248541A1

公开(公告)日：2022-08-04

申请号：US17164458

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik KIM ,  Changhan Hobie YUN ,  Paragkumar Ajaybhai THADESAR ,  Nosun PARK ,  Sameer Sunil VADHAVKAR

IPC: H05K5/00 ,  H01R12/72 ,  H01R43/20

Abstract: Certain aspects of the present disclosure generally relate to an electronic device. One example electronic device generally includes a SIP module having a circuit board and one or more electronic elements disposed above the circuit board, and one or more first connector contacts coupled to a bottom surface of the circuit board, the one or more first connector contacts being configured to electrically couple the circuit board to a connector receptacle.

公开(公告)号：US20210375732A1

公开(公告)日：2021-12-02

申请号：US16890376

申请日：2020-06-02

Applicant: QUALCOMM Incorporated

Inventor： Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR ,  Francesco CARRARA ,  Daniel Daeik KIM

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

Abstract: Certain aspects of the present disclosure generally relate to a dielectric removal methodology and a metal patterning approach to allow partial embedding of electronic components (e.g., surface mount devices (SMDs)) in a substrate. By partially embedding relatively taller SMDs, the overall height of an electronic device may be reduced.

公开(公告)号：US20200091094A1

公开(公告)日：2020-03-19

申请号：US16132323

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Niranjan Sunil MUDAKATTE ,  Wei-Chuan CHEN ,  Paragkumar Ajaybhai THADESAR ,  Christopher POLLOCK ,  Xiaoju YU ,  Rongguo ZHOU ,  Kai LIU ,  Jonghae KIM

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/15 ,  H03H9/54 ,  H03H9/64 ,  H03H7/01 ,  H03H3/02 ,  H03H3/08

Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.