公开(公告)号：US20210098320A1

公开(公告)日：2021-04-01

申请号：US16590299

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Daniel GARCIA ,  Kinfegebriel Amera MENGISTIE ,  Francesco CARRARA ,  Chang-Ho LEE ,  Ashish ALAWANI ,  Mark KUHLMAN ,  John Jong-Hoon LEE ,  Jeongkeun KIM ,  Xiaoju YU ,  Supatta NIRAMARNKARN

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

公开(公告)号：US20230223362A1

公开(公告)日：2023-07-13

申请号：US17575492

申请日：2022-01-13

Applicant: QUALCOMM Incorporated

Inventor： FNU SURAJ PRAKASH ,  Paragkumar Ajaybhai THADESAR ,  John Jong-Hoon LEE ,  Nikhil RAMAN ,  Peng SONG ,  Francesco CARRARA

IPC: H01L23/64 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/528 ,  H01L28/10

Abstract: A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor through the second inductor.

公开(公告)号：US20210375732A1

公开(公告)日：2021-12-02

申请号：US16890376

申请日：2020-06-02

Applicant: QUALCOMM Incorporated

Inventor： Paragkumar Ajaybhai THADESAR ,  Sameer Sunil VADHAVKAR ,  Francesco CARRARA ,  Daniel Daeik KIM

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

Abstract: Certain aspects of the present disclosure generally relate to a dielectric removal methodology and a metal patterning approach to allow partial embedding of electronic components (e.g., surface mount devices (SMDs)) in a substrate. By partially embedding relatively taller SMDs, the overall height of an electronic device may be reduced.