公开(公告)号：US11450359B1

公开(公告)日：2022-09-20

申请号：US17366864

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao Chen ,  Po-Hung Chen ,  Chen-ju Hsieh ,  David Li ,  Chulmin Jung ,  Ayan Paul

IPC: G11C7/10 ,  G11C7/12 ,  H03K19/173 ,  G11C5/14 ,  H03K19/0185

Abstract: Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.

公开(公告)号：US10325648B2

公开(公告)日：2019-06-18

申请号：US15379285

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Darshit Mehta ,  Chulmin Jung ,  Po-Hung Chen

IPC: G11C11/00 ,  G11C11/419 ,  G06F3/06 ,  G11C7/10

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.