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    High-speed word line decoder and level-shifter
    2.
    发明授权
    High-speed word line decoder and level-shifter 有权

    公开(公告)号：US09940987B2

    公开(公告)日：2018-04-10

    申请号：US15070963

    申请日：2016-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/06 ,  G11C5/14

    CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

    Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

    Memory write methods and circuits
    4.
    发明授权
    Memory write methods and circuits 有权

    公开(公告)号：US11450359B1

    公开(公告)日：2022-09-20

    申请号：US17366864

    申请日：2021-07-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiao Chen ,  Po-Hung Chen ,  Chen-ju Hsieh ,  David Li ,  Chulmin Jung ,  Ayan Paul

    IPC: G11C7/10 ,  G11C7/12 ,  H03K19/173 ,  G11C5/14 ,  H03K19/0185

    Abstract: Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.

    HIGH SPEED DEGLITCH SENSE AMPLIFIER
    5.
    发明申请
    HIGH SPEED DEGLITCH SENSE AMPLIFIER 审中-公开
    高速度感应放大器

    公开(公告)号：US20150294697A1

    公开(公告)日：2015-10-15

    申请号：US14251315

    申请日：2014-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Rui Li ,  David Li ,  Tahseen Shakir ,  Sei Seung Yoon

    IPC: G11C7/06 ,  G11C11/419

    CPC classification number: G11C7/065 ,  G11C11/419

    Abstract: A sense amplifier is provided that includes a skewed latch that latches a voltage difference developed responsive to a read operation on an accessed memory cell. The skewed latch includes a loaded logic gate that is cross-coupled with an unloaded logic gate. The loaded logic gate drives the unloaded logic gate and an output transistor whereas the unloaded logic gate drives only the loaded logic gate.

    Abstract translation: 提供了一种读出放大器，其包括倾斜的锁存器，其锁存响应于对所访问的存储器单元的读取操作产生的电压差。 偏斜锁存器包括与卸载逻辑门交叉耦合的加载逻辑门。 加载的逻辑门驱动无载逻辑门和输出晶体管，而无负载逻辑门仅驱动加载的逻辑门。

    Memory circuit architecture
    6.
    发明授权
    Memory circuit architecture 有权

    公开(公告)号：US11600307B2

    公开(公告)日：2023-03-07

    申请号：US17136616

    申请日：2020-12-29

    Applicant: QUALCOMM Incorporated

    Inventor： David Li ,  Rahul Biradar ,  Biju Manakkam Veetil ,  Po-Hung Chen ,  Ayan Paul ,  Sung Son ,  Shivendra Kushwaha ,  Ravindra Reddy Chekkera ,  Derek Yang

    IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

    Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

    High-speed level shifter
    7.
    发明授权
    High-speed level shifter 有权

    公开(公告)号：US09997208B1

    公开(公告)日：2018-06-12

    申请号：US15473124

    申请日：2017-03-29

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  Fahad Ahmed ,  Changho Jung ,  Sei Seung Yoon ,  David Li

    IPC: G11C8/08 ,  G11C5/14 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/12

    CPC classification number: G11C5/147 ,  G11C7/12 ,  G11C8/10 ,  H03K3/356069 ,  H03K19/018528

    Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

    HIGH-SPEED WORD LINE DECODER AND LEVEL-SHIFTER
    8.
    发明申请
    HIGH-SPEED WORD LINE DECODER AND LEVEL-SHIFTER 有权
    高速字线解码器和电平变换器

    公开(公告)号：US20160276005A1

    公开(公告)日：2016-09-22

    申请号：US15070963

    申请日：2016-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

    IPC: G11C8/08 ,  G11C8/10 ,  G11C5/14

    CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

    Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

    Abstract translation: 提供了一种存储器，其包括行解码器，其将地址解码为用于从多个字线选择要断言的字线的多个解码信号。 每个字线通过处理解码信号的解码器电平转换器驱动。 每个解码器电平转换器对应于解码信号的唯一组合。 行解码器处于逻辑功率域，使得解码信号被断言为逻辑电源电压。 当解码器电平移位器的解码信号的唯一组合由行解码器确定时，解码器电平转换器用存储器电源域的存储器电源电压驱动相应的字线。

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