公开(公告)号：US11184197B2

公开(公告)日：2021-11-23

申请号：US16418358

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US20190266112A1

公开(公告)日：2019-08-29

申请号：US16290346

申请日：2019-03-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.