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    Data stream router
    12.
    发明授权
    Data stream router 有权
    数据流路由器

    公开(公告)号：US08571045B2

    公开(公告)日：2013-10-29

    申请号：US12681251

    申请日：2008-10-02

    申请人： Robby Gurdan ,  Richard Foss

    发明人： Robby Gurdan ,  Richard Foss

    IPC分类号： H04L12/28 ,  H04J3/16 ,  G06F11/00 ,  G08C15/08 ,  G01R31/08

    CPC分类号： H04L12/4637 ,  G10H1/0066 ,  G10H1/46 ,  H04H60/04 ,  H04L67/125 ,  H04L67/28 ,  H04L67/2823 ,  H04L69/16 ,  H04L69/26 ,  H04N21/23602 ,  H04N21/2381 ,  H04N21/4342 ,  H04N21/4345 ,  H04N21/4381

    摘要： The present invention concerns a router for providing isochronous data transfer and asynchronous data transfer on the basis of a predetermined protocol between devices of different network sections connected to the router, when a connection management application executed by the router translates a user request to transfer data from a transmitting device of a first network section to a receiving device of a second network section into commands of the protocol for establishing a first data connection between the transmitting device and the router and a second data connection between the router and the receiving device when the data is transferred from the transmitting device via the established data connections to the receiving device.

    摘要翻译： 本发明涉及一种用于在连接到路由器的不同网络部分的设备之间的预定协议的基础上提供等时数据传输和异步数据传输的路由器，当由路由器执行的连接管理应用程序转换用户请求以从 将第一网络部分的发送装置连接到第二网络部分的接收装置，转换成用于在发送装置和路由器之间建立第一数据连接的协议命令，以及当数据在路由器和接收装置之间时的第二数据连接 通过建立的数据连接从发送设备传送到接收设备。

    Error correction scheme for memory
    13.
    发明授权
    Error correction scheme for memory 有权
    内存误差校正方案

    公开(公告)号：US07266747B2

    公开(公告)日：2007-09-04

    申请号：US10694761

    申请日：2003-10-29

    申请人： Richard Foss

    发明人： Richard Foss

    IPC分类号： H03M13/00

    CPC分类号： H03M13/29 ,  G06F11/1044 ,  H03M13/095

    摘要： An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

    摘要翻译： 用于清除数据错误的嵌入式DRAM ECC架构。 嵌入式DRAM ECC架构基于二维线性奇偶校验方案，并且包括多个存储块和奇偶校验块。 每个存储块包括用于存储行奇偶校验位的附加列，并且奇偶校验块存储列奇偶校验位。 与每个存储器的现有局部数据总线并联耦合的行奇偶校验电路在刷新或读取操作期间检查本地数据总线位与奇偶校验位的奇偶校验，以识别奇偶校验故障。 通过将每个存储器块的本地数据总线的数据迭代地传送到现有的全局数据总线上，并通过列奇偶校验电路检查全局数据总线上的奇偶校验来实现字的不正确位的识别。 当检测到全局数据总线奇偶校验故障时，全局数据总线的所有位都被反相，以通过本地数据总线从存储块中清除错误的位。

    Method and circuit for error correction in CAM cells
    14.
    发明申请
    Method and circuit for error correction in CAM cells 失效
    CAM单元纠错方法与电路

    公开(公告)号：US20060123327A1

    公开(公告)日：2006-06-08

    申请号：US11313661

    申请日：2005-12-22

    申请人： Richard Foss ,  Alan Roth

    发明人： Richard Foss ,  Alan Roth

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： G06F11/1064 ,  G11C15/00

    摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.

    摘要翻译： 提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。 阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。 该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

    Method and apparatus for replacing defective rows in a semiconductor memory array
    15.
    发明授权
    Method and apparatus for replacing defective rows in a semiconductor memory array 有权
    用于替换半导体存储器阵列中的有缺陷的行的方法和装置

    公开(公告)号：US06888731B2

    公开(公告)日：2005-05-03

    申请号：US10306734

    申请日：2002-11-29

    申请人： Alan Roth ,  Douglas Perry ,  Richard Foss

    发明人： Alan Roth ,  Douglas Perry ,  Richard Foss

    IPC分类号： G11C15/00 ,  G11C29/00 ,  G11C15/02

    CPC分类号： G11C29/848 ,  G11C15/00

    摘要： A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row match line input, repeating the switching for subsequent matchlines upto the matchline of the at least one spare row.

    摘要翻译： 一种用于替换CAM阵列中的有缺陷的行的方法，所述阵列具有多个正常的单元行和至少一个备用的单元行，每一行由相应的字线信号使能，并且具有对应的匹配线输出 到匹配行解码器中的多个匹配线输入中的对应的一个，该方法包括以下步骤：（a）产生指示阵列中缺陷行的位置的信号; （b）产生用于选择多个正常行中的一个的一组字线选择信号; （d）使用缺陷行信号将缺陷行的字线选择信号切换到与缺陷行相邻的行，并将相邻行字线选择信号切换到至少一个备用行的后续行，以及（e） 使用有缺陷的行信号将与缺陷行相邻的行的匹配线输入切换到缺陷行的匹配线输入，并将随后的行匹配线输入切换到相邻行匹配线输入，重复对后续匹配线的切换直到 至少一个备用行的匹配线。

    Digital multimedia network with latency control
    17.
    发明授权
    Digital multimedia network with latency control 有权
    具有延迟控制的数字多媒体网络

    公开(公告)号：US08477812B2

    公开(公告)日：2013-07-02

    申请号：US12681208

    申请日：2008-10-02

    申请人： Robby Gurdan ,  Richard Foss

    发明人： Robby Gurdan ,  Richard Foss

    IPC分类号： H04J3/06

    CPC分类号： H04L12/4637 ,  G10H1/0066 ,  G10H1/46 ,  H04H60/04 ,  H04L67/125 ,  H04L67/28 ,  H04L67/2823 ,  H04L69/16 ,  H04L69/26 ,  H04N21/23602 ,  H04N21/2381 ,  H04N21/4342 ,  H04N21/4345 ,  H04N21/4381

    摘要： The present invention relates to a digital multimedia network 1 with latency control comprising apparatuses for processing of data streams, wherein a borderline input apparatus providing a data stream generates a latency time stamp (LTS) which contains an absolute time indicating a creation time of said data stream and an accumulated delay time which is updated by each apparatus processing said data stream, wherein said latency time stamp (LTS) of said data stream is evaluated by a borderline output apparatus of said network which synchronizes said data stream.

    摘要翻译： 本发明涉及具有等待时间控制的数字多媒体网络1，其包括用于处理数据流的装置，其中提供数据流的边界线输入装置产生等待时间戳（LTS），其包含指示所述数据的创建时间的绝对时间 流和由每个处理所述数据流的设备更新的累积延迟时间，其中所述数据流的所述等待时间戳（LTS）由同步所述数据流的所述网络的边界输出设备来评估。

    DATA STREAM ROUTER
    19.
    发明申请
    DATA STREAM ROUTER 有权
    数据流路由器

    公开(公告)号：US20100284417A1

    公开(公告)日：2010-11-11

    申请号：US12681251

    申请日：2008-10-02

    申请人： Robby Gurdan ,  Richard Foss

    发明人： Robby Gurdan ,  Richard Foss

    IPC分类号： H04L12/56

    CPC分类号： H04L12/4637 ,  G10H1/0066 ,  G10H1/46 ,  H04H60/04 ,  H04L67/125 ,  H04L67/28 ,  H04L67/2823 ,  H04L69/16 ,  H04L69/26 ,  H04N21/23602 ,  H04N21/2381 ,  H04N21/4342 ,  H04N21/4345 ,  H04N21/4381

    摘要： The invention provides a router for providing isochronous data transfer and asynchronous data transfer on the basis of a predetermined protocol between devices of different network sections connected to said router, wherein a connection management application executed by said router translates a user request to transfer data from a transmitting device of a first network section to a receiving device of a second network section into commands of said protocol for establishing a first data connection between said transmitting device and said router and a second data connection between said router and said receiving device, wherein said data is transferred from said transmitting device via the established data connections to said receiving device.

    摘要翻译： 本发明提供一种路由器，用于根据连接到所述路由器的不同网络部分的设备之间的预定协议提供同步数据传输和异步数据传输，其中由所述路由器执行的连接管理应用程序转换用户请求以从 将第一网络部分的发送设备发送到第二网络部分的接收设备，以形成所述协议的命令，用于在所述发送设备和所述路由器之间建立第一数据连接以及所述路由器与所述接收设备之间的第二数据连接，其中所述数据 经由建立的数据连接从所述发送设备传送到所述接收设备。

    Error correction scheme for memory
    20.
    发明授权
    Error correction scheme for memory 有权
    内存误差校正方案

    公开(公告)号：US07636880B2

    公开(公告)日：2009-12-22

    申请号：US11830077

    申请日：2007-07-30

    申请人： Richard Foss

    发明人： Richard Foss

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： H03M13/29 ,  G06F11/1044 ,  H03M13/095

    摘要： An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

    摘要翻译： 用于清除数据错误的嵌入式DRAM ECC架构。 嵌入式DRAM ECC架构基于二维线性奇偶校验方案，并且包括多个存储块和奇偶校验块。 每个存储块包括用于存储行奇偶校验位的附加列，并且奇偶校验块存储列奇偶校验位。 与每个存储器的现有局部数据总线并联耦合的行奇偶校验电路在刷新或读取操作期间检查本地数据总线位与奇偶校验位的奇偶校验，以识别奇偶校验故障。 通过将每个存储器块的本地数据总线的数据迭代地传送到现有的全局数据总线上，并通过列奇偶校验电路检查全局数据总线上的奇偶校验来实现字的不正确位的识别。 当检测到全局数据总线奇偶校验故障时，全局数据总线的所有位都被反相，以通过本地数据总线从存储块中清除错误的位。