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32 条记录 (耗时 0.023 秒)

    Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions
    14.
    发明授权
    Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions 失效
    用于实现PCI对等功能的订购机制，订购方法和计算机程序产品

    公开(公告)号：US06529991B1

    公开(公告)日：2003-03-04

    申请号：US09310797

    申请日：1999-05-12

    申请人： Bruce Leroy Beukema ,  Ronald Edward Fuhs ,  Kenneth Claude Hinz

    发明人： Bruce Leroy Beukema ,  Ronald Edward Fuhs ,  Kenneth Claude Hinz

    IPC分类号： G06F1320

    CPC分类号： G06F13/423 ,  G06F13/1621

    摘要： An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read command is sent. Responsive to sending the read command; checking for the retry read received command is provided. Responsive to identifying the retry read received command, the read command is resent.

    摘要翻译： 提供了一种用于实现PCI局部总线（PCI）对等功能的排序机制，排序方法和计算机程序产品。 当接收到读命令时，执行检查可用资源。 响应于不识别可用资源，发送重试读取命令。 响应发送读命令; 提供检查重试读取命令。 响应于识别重试读取命令，读取命令被重新发送。

    Apparatus, system and method for controlling access to facilities based on usage classes
    16.
    发明授权
    Apparatus, system and method for controlling access to facilities based on usage classes 有权
    基于使用类别控制对设施的访问的装置，系统和方法

    公开(公告)号：US07010633B2

    公开(公告)日：2006-03-07

    申请号：US10411447

    申请日：2003-04-10

    申请人： Richard Louis Arndt ,  Bruce Leroy Beukema ,  David F. Craddock ,  Ronald Edward Fuhs ,  Thomas Anthony Gregg ,  Bruce Marshall Walk

    发明人： Richard Louis Arndt ,  Bruce Leroy Beukema ,  David F. Craddock ,  Ronald Edward Fuhs ,  Thomas Anthony Gregg ,  Bruce Marshall Walk

    IPC分类号： G06F13/14 ,  G06F15/173

    CPC分类号： G06F12/1491

    摘要： An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

    摘要翻译： 提供了一种用于基于请求者的使用类来控制对设施的访问的装置，系统和方法。 利用设备，系统和方法，提供了一种保护主机通道适配器（HCA）设施免受未经授权访问的两级保护机制。 利用本发明，通过虚拟地址转换提供第一级别的访问，以及用于确定访问请求者是否可访问与虚拟地址映射到的实际地址相关联的系统存储器地址空间页面的机制。 通过分配使用类别并确定访问HCA设施所需的使用类别来提供第二级别的访问。

    Moving hardware context structures in memory while maintaining system operation
    18.
    发明授权
    Moving hardware context structures in memory while maintaining system operation 有权
    在维护系统运行的同时，在内存中移动硬件上下文结构

    公开(公告)号：US07475209B2

    公开(公告)日：2009-01-06

    申请号：US10845498

    申请日：2004-05-13

    申请人： Ronald Edward Fuhs ,  Ryan Scott Haraden ,  Bruce Marshall Walk

    发明人： Ronald Edward Fuhs ,  Ryan Scott Haraden ,  Bruce Marshall Walk

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0223

    摘要： An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.

    摘要翻译： 适配器包括寄存器，本地上下文表和逻辑，其允许在计算机系统继续运行时将硬件上下文结构从存储器中的第一位置复制到存储器中的第二位置。 适配器中的本地上下文表从内存中的第一个位置加载了所需的上下文条目块。 寄存器中的值使适配器以不阻碍计算机系统操作的方式将上述条目的所需块写入存储器中的第二个位置。

    Specifying wrap register for storing memory address to store completion status of instruction to external device
    19.
    发明授权
    Specifying wrap register for storing memory address to store completion status of instruction to external device 失效
    指定用于存储存储器地址的包装寄存器，以将指令的完成状态存储到外部设备

    公开(公告)号：US06275876B1

    公开(公告)日：2001-08-14

    申请号：US09316243

    申请日：1999-05-21

    申请人： Kenneth Michael Valk ,  Thomas Rembert Sand ,  Ronald Edward Fuhs ,  Gregory Michael Nordstrom ,  Bruce Leroy Beukema

    发明人： Kenneth Michael Valk ,  Thomas Rembert Sand ,  Ronald Edward Fuhs ,  Gregory Michael Nordstrom ,  Bruce Leroy Beukema

    IPC分类号： G06F1312

    CPC分类号： G06F13/126

    摘要： A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

    摘要翻译： 计算系统包括处理系统，至少第一寄存器和控制系统。 处理系统产生第一指令集和第一地址，用于存储第一指令集的第一完成状态。 第一个寄存器从处理系统接收第一个地址。 控制系统将从处理系统接收的第一指令集传送到外部设备。 控制系统从外部设备接收第一完成状态，访问第一寄存器以确定第一指令集的第一地址，并将第一完成状态存储在所确定的第一地址中。