公开(公告)号：US20240179069A1

公开(公告)日：2024-05-30

申请号：US18431526

申请日：2024-02-02

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Bjørn Dag Johnsen ,  Ajoy Siddabathuni ,  David Brean

IPC: H04L41/12 ,  H04L45/18 ,  H04L45/48 ,  H04L49/25 ,  H04L49/356

CPC classification number: H04L41/12 ,  H04L45/18 ,  H04L45/48 ,  H04L49/252 ,  H04L49/358

Abstract: Systems and methods for using InfiniBand routing algorithms for Ethernet fabrics in a high performance computing environment. The method can provide, at a computer comprising one or more microprocessors, a plurality of switches, a plurality of hosts, a topology provider (TP) module, a routing engine (RE) module, and a switch initializer (SI) module. The method can perform a discovery sweep, by the TP, of the plurality of hosts and the plurality of switches and assigns an address to each of the plurality of hosts and the plurality of switches. The method can calculate, by the routing engine, a routing map, based upon a routing scheme, for the plurality of hosts and the plurality of switches, the routing map comprising a plurality of forwarding tables. The method can configure, each of the plurality of switches with a forwarding table of the plurality of forwarding tables calculated by the routing engine.

公开(公告)号：US11824749B2

公开(公告)日：2023-11-21

申请号：US17520273

申请日：2021-11-05

Applicant: Oracle International Corporation

Inventor： Bjørn Dag Johnsen ,  Arvind Srinivasan ,  Brian Manula

IPC: H04L43/0876 ,  G06F9/451 ,  H04L45/745 ,  G06F11/30 ,  G11C15/00 ,  H04L47/20 ,  H04L67/1097 ,  H04L49/25 ,  H04L49/356 ,  H04L69/22 ,  H04L47/70

CPC classification number: H04L43/0876 ,  G06F9/451 ,  G06F11/3006 ,  G11C15/00 ,  H04L45/74591 ,  H04L47/20 ,  H04L47/70 ,  H04L49/25 ,  H04L49/358 ,  H04L67/1097 ,  H04L69/22 ,  G06F2201/88

Abstract: System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.

公开(公告)号：US11716292B2

公开(公告)日：2023-08-01

申请号：US17370580

申请日：2021-07-08

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Dag Georg Moxnes ,  Line Holen ,  Bjørn Dag Johnsen

IPC: H04L49/25 ,  H04L49/10 ,  H04L67/10 ,  G06F9/451 ,  G06F16/22 ,  H04L49/356 ,  H04L45/48 ,  H04L41/0853 ,  H04L43/0817 ,  H04L41/046 ,  H04L43/0823 ,  H04L43/0882 ,  H04L41/0803 ,  H04L41/12 ,  H04L49/15 ,  H04L49/00 ,  H04L45/02 ,  H04L67/1097 ,  G06F9/455 ,  H04L41/14 ,  H04L9/40 ,  H04L12/44

CPC classification number: H04L49/25 ,  G06F9/451 ,  G06F9/45558 ,  G06F16/2237 ,  H04L41/046 ,  H04L41/0803 ,  H04L41/0853 ,  H04L41/12 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0823 ,  H04L43/0882 ,  H04L45/02 ,  H04L45/48 ,  H04L49/10 ,  H04L49/15 ,  H04L49/30 ,  H04L49/358 ,  H04L49/70 ,  H04L63/20 ,  H04L67/10 ,  H04L67/1097 ,  G06F2009/45579 ,  G06F2009/45595 ,  H04L12/44 ,  H04L63/12

Abstract: System and method for supporting scalable representation of switch port status in a high performance computing environment. In accordance with an embodiment, a scalable representation of switch port status can be provided. By adding a scalable representation of switch port status at each switch (both physical and virtual)—instead of getting all switch port changes individually, the scalable representation of switch port status can combine a number of ports that can scale by just using a few bits of information for each port's status.

公开(公告)号：US11695583B2

公开(公告)日：2023-07-04

申请号：US17464806

申请日：2021-09-02

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Bjørn Dag Johnsen ,  Line Holen ,  Dag Georg Moxnes

IPC: H04L41/14 ,  H04L41/0853 ,  H04L41/0893 ,  H04L49/356 ,  H04L12/18 ,  H04L41/00 ,  H04L45/48 ,  G06F16/22 ,  H04L61/103 ,  H04L61/5069 ,  H04L45/16 ,  H04L47/36 ,  H04L49/15 ,  G06F9/455 ,  H04L45/021 ,  H04L67/10 ,  H04L49/201 ,  H04L61/10 ,  H04L69/18 ,  H04L101/668 ,  H04L101/622 ,  H04L49/00

CPC classification number: H04L12/185 ,  G06F9/45558 ,  G06F16/2255 ,  H04L12/1886 ,  H04L41/0853 ,  H04L41/0893 ,  H04L41/14 ,  H04L41/30 ,  H04L45/021 ,  H04L45/16 ,  H04L45/48 ,  H04L47/36 ,  H04L49/15 ,  H04L49/201 ,  H04L49/356 ,  H04L49/357 ,  H04L49/358 ,  H04L61/10 ,  H04L61/103 ,  H04L61/5069 ,  H04L67/10 ,  H04L69/18 ,  G06F2009/4557 ,  G06F2009/45595 ,  H04L49/30 ,  H04L2101/622 ,  H04L2101/668

Abstract: Systems and methods for InfiniBand fabric optimizations to minimize SA access and startup failover times. A system can comprise one or more microprocessors, a first subnet, the first subnet comprising a plurality of switches, a plurality of host channel adapters, a plurality of hosts, and a subnet manager, the subnet manager running on one of the one or more switches and the plurality of host channel adapters. The subnet manager can be configured to determine that the plurality of hosts and the plurality of switches support a same set of capabilities. On such determination, the subnet manager can configure an SMA flag, the flag indicating that a condition can be set for each of the host channel adapter ports.

公开(公告)号：US20190230037A1

公开(公告)日：2019-07-25

申请号：US16259228

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： ALBERT S. CHENG ,  THOMAS D. LOVETT ,  MICHAEL A. PARKER

IPC: H04L12/851 ,  H04L12/911 ,  H04L12/931 ,  H04L12/715 ,  H04L12/26

CPC classification number: H04L47/24 ,  H04L43/0894 ,  H04L45/64 ,  H04L47/2433 ,  H04L47/245 ,  H04L47/283 ,  H04L47/822 ,  H04L49/358

Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

公开(公告)号：US20190007346A1

公开(公告)日：2019-01-03

申请号：US16104503

申请日：2018-08-17

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Bjørn Dag Johnsen ,  Dag Georg Moxnes ,  Bartosz Bogdanski

IPC: H04L12/931 ,  H04L29/08 ,  H04L12/761 ,  H04L12/751

CPC classification number: H04L49/358 ,  H04L45/02 ,  H04L45/16 ,  H04L45/48 ,  H04L45/66 ,  H04L49/201 ,  H04L67/1097 ,  H04L67/2842 ,  H04L69/22

Abstract: Systems and methods to use all incoming multicast (MC) packets as a basis for global unique identifier (GUID) to local identifier (LID) cache contents in a high performance computing environment, in accordance with an embodiment. Since all multicast packets have a Global Route Header (GRH), there is always both a source GID and a source LID defined for an incoming multicast packet. This implies that it is, in general, possible for an HCA implementation to gather information about GID and GUID to LID mappings for any sender node based on all incoming MC packets.

公开(公告)号：US20180234383A1

公开(公告)日：2018-08-16

申请号：US15379065

申请日：2016-12-14

Applicant: Raytheon Company

Inventor： Brandon H. Daugherty ,  Jason B. Emery ,  Brian D. Sirois ,  Bradley D. Staal ,  Paul J. Lewis ,  Michael S. Mitchener

IPC: H04L29/12 ,  H03K19/177 ,  G06F17/50 ,  G06F13/38 ,  H04L12/54 ,  H03K19/173 ,  H04L29/06

CPC classification number: H04L61/10 ,  G06F13/385 ,  G06F17/5054 ,  H03K19/1733 ,  H03K19/17708 ,  H03K19/17748 ,  H04L12/56 ,  H04L49/358 ,  H04L67/06 ,  H04L69/161 ,  H04L69/164

Abstract: A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.

公开(公告)号：US20180167274A1

公开(公告)日：2018-06-14

申请号：US15891183

申请日：2018-02-07

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Evangelos Tasoulas ,  Ernst Gunnar Gran ,  Tor Skeie ,  Bjørn Dag Johnsen

IPC: H04L12/24 ,  H04L12/931 ,  H04L12/933 ,  H04L12/44

CPC classification number: H04L41/0813 ,  G06F9/5077 ,  H04L12/44 ,  H04L41/083 ,  H04L41/0836 ,  H04L49/10 ,  H04L49/15 ,  H04L49/358

Abstract: A hybrid reconfiguration scheme can allow for fast partial network reconfiguration with different routing algorithms of choice in different subparts of the network. Partial reconfigurations can be orders of magnitude faster than the initial full configuration, thus making it possible to consider performance-driven reconfigurations in lossless networks.

公开(公告)号：US09864759B2

公开(公告)日：2018-01-09

申请号：US13170490

申请日：2011-06-28

Applicant: Ballav Bihani ,  Patrik Torstensson ,  Adam Messinger ,  Naresh Revanuru

Inventor： Ballav Bihani ,  Patrik Torstensson ,  Adam Messinger ,  Naresh Revanuru

IPC: G06F12/00 ,  G06F17/30 ,  H04L29/06 ,  G06F15/173 ,  H04L12/24 ,  H04L12/931 ,  H04L29/08 ,  G06F9/455

CPC classification number: G06F17/30286 ,  G06F9/45504 ,  G06F15/17318 ,  G06F17/30368 ,  G06F17/30584 ,  H04L29/06088 ,  H04L41/042 ,  H04L41/0686 ,  H04L49/358 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1004 ,  H04L67/1027 ,  H04L67/1034 ,  H04L67/1095 ,  H04L67/14 ,  H04L67/142 ,  H04L67/146

Abstract: Systems and methods are provided for providing scatter/gather data processing. In accordance with an embodiment, a such a system can include a cluster of one or more high performance computing systems, each including one or more processors and a high performance memory. The cluster communicates over an InfiniBand network. The system can also include a middleware environment, executing on the cluster, that includes one or more application server instances. The system can further include a plurality of muxers. Each application server instance includes at least one muxer, and each muxer is operable to collect data from a plurality of locations in the high performance memory, and transfer the data in bulk.

公开(公告)号：US20170324681A1

公开(公告)日：2017-11-09

申请号：US15656856

申请日：2017-07-21

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Bjørn Dag Johnsen ,  Arvind Srinivasan ,  Shimon Muller

IPC: H04L12/931 ,  H04L12/935 ,  H04L12/933 ,  H04L29/08 ,  G06F17/30 ,  H04L12/751 ,  H04L12/26

CPC classification number: H04L49/358 ,  G06F16/2237 ,  G06F2201/88 ,  H04L43/0882 ,  H04L45/02 ,  H04L47/20 ,  H04L49/10 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/70 ,  H04L67/10

Abstract: System and method for supporting a partitioned switch forwarding table in a high performance computing environment. Described methods and systems can support partitioned switch forwarding tables (e.g., partitioned LFTs) by setting up hardware registers that divide the LFT into at least two partitions, a first partition that supports legacy forwarding (e.g., standard LID based forwarding without the need to use portions of the GRH), and a second partition to support the GRH based forwarding that is described above. In such a manner, switches and other hardware within a core fabric can behave as legacy nodes/switches having standard LFTs, while also being able to support the extended addressing supplied through the use of portions of the GRH.