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公开(公告)号：US20210397481A1
公开(公告)日：2021-12-23
申请号：US17145958
申请日：2021-01-11
Inventor： Wookeun JUNG , Jaejin LEE , Seung Wook LEE
Abstract: A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.
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公开(公告)号：US20210373944A1
公开(公告)日：2021-12-02
申请号：US17170109
申请日：2021-02-08
Inventor： Seung Wook LEE , Jae Wook LEE , Young Hwan OH , Seng Hak KIM , Tae Jun HAM
Abstract: A scheduler, a method of operating the scheduler, and an accelerator apparatus including the scheduler are disclosed. A method of operating a scheduler to perform scheduling on models to be executed in an accelerator, the method includes receiving at least one execution request for a first model and a second model that are executed independently from each other in the accelerator, and performing layer-unit scheduling on the first model and the second model based on workload characteristics of the first model and the second model.
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Patent Agency Ranking
公开(公告)号：US20210089610A1
公开(公告)日：2021-03-25
申请号：US16856380
申请日：2020-04-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyung-Dal KWON , Seung Wook LEE
Abstract: A memory device includes a memory configured to store input data and filter data for a convolution operation, and a function processor configured to, in response to a read command of at least a portion of data from among the input data and the filter data, transform the at least a portion of the data based on a parameter of the convolution operation during a clock cycle corresponding to the read command and output a corresponding transformation result as transformed data.
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公开(公告)号：US20160099267A1
公开(公告)日：2016-04-07
申请号：US14872691
申请日：2015-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung Wook LEE , Yi Tae KIM , Jong Eun PARK , Jung Chak AHN , Kyung Ho LEE , Tae Hun LEE , Hee Geun JEONG
IPC: H01L27/146 , H04N9/04 , H04N5/374
CPC classification number: H01L27/1463 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14689 , H04N5/374 , H04N9/045
Abstract: An image sensor such as a complementary metal-oxide-semiconductor (CMOS) image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate including a first surface and a third surface formed by removing a part of the semiconductor substrate from a second surface opposite to the first surface; a plurality of active regions which are formed between the first surface and the third surface and each of which includes a photoelectric conversion element generating charges in response to light input through the third surface; and an isolation region vertically formed from either of the first and third surfaces to isolate the active regions from one another. When the CMOS image sensor is viewed from the above of the third surface, each of the active regions may have round corners and concave sides.
Abstract translation: 提供了诸如互补金属氧化物半导体（CMOS）图像传感器的图像传感器及其制造方法。 CMOS图像传感器包括：半导体衬底，其包括通过从与第一表面相对的第二表面去除半导体衬底的一部分而形成的第一表面和第三表面; 多个有源区，形成在第一表面和第三表面之间，每个有源区包括响应于通过第三表面输入的光而产生电荷的光电转换元件; 以及从所述第一表面和所述第三表面中的任一个垂直地形成的隔离区域，以将所述活性区域彼此隔离。 当从第三表面的上方观察CMOS图像传感器时，每个有源区域可以具有圆角和凹面。
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公开(公告)号：US20230333899A1
公开(公告)日：2023-10-19
申请号：US18337723
申请日：2023-06-20
Inventor： Wookeun JUNG , Jaejin LEE , Seung Wook LEE
CPC classification number: G06F9/5027 , G06F9/3802 , G06N3/063 , G06F9/48 , G06F9/3836 , G06F9/30014
Abstract: A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.
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公开(公告)号：US20220365891A1
公开(公告)日：2022-11-17
申请号：US17876116
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION
Inventor： Seung Wook LEE , Hweesoo KIM , Jung Ho AHN
Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
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公开(公告)号：US20220114116A1
公开(公告)日：2022-04-14
申请号：US17192032
申请日：2021-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION
Inventor： Seung Wook LEE , Hweesoo KIM , Jung Ho AHN
Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
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