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公开(公告)号：US20240061972A1
公开(公告)日：2024-02-22
申请号：US18181604
申请日：2023-03-10
发明人： Hyung-Dal KWON , Byeonghyun KO , Seongbeom KIM , Jaejin LEE , Gyeongje CHO
IPC分类号： G06F30/20
CPC分类号： G06F30/20
摘要： An apparatus for modelling a computing system including a processor configured to generate a plurality of classes related to properties of a computing system based on received information related to a first hardware of the computing system, generate a profile result based on the plurality of classes, and predict a performance of second hardware in the computing system in place of the first hardware, the prediction being based on the profile result.
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公开(公告)号：US20210397557A1
公开(公告)日：2021-12-23
申请号：US17148676
申请日：2021-01-14
发明人： Jaejin LEE , Heehoon KIM , Seung Wook LEE
IPC分类号： G06F12/0862 , G06N3/08 , G06F12/0842
摘要： An accelerator includes processing elements configured to perform an operation associated with an instruction received from a host processor, hierarchical memories configured to be accessible by any one or any combination of any two or more of the processing elements, and sub-cores configured to prefetch data associated with the operation to a memory of a corresponding level of the hierarchical memories.
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公开(公告)号：US20210397481A1
公开(公告)日：2021-12-23
申请号：US17145958
申请日：2021-01-11
发明人： Wookeun JUNG , Jaejin LEE , Seung Wook LEE
摘要： A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.
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公开(公告)号：US20230333899A1
公开(公告)日：2023-10-19
申请号：US18337723
申请日：2023-06-20
发明人： Wookeun JUNG , Jaejin LEE , Seung Wook LEE
CPC分类号： G06F9/5027 , G06F9/3802 , G06N3/063 , G06F9/48 , G06F9/3836 , G06F9/30014
摘要： A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.
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公开(公告)号：US20140297992A1
公开(公告)日：2014-10-02
申请号：US14228868
申请日：2014-03-28
发明人： Jin-Seok LEE , Seong-Gun KIM , Dong-Hoon YOO , Seok-Joong HWANG , Jeongho NAH , Jaejin LEE , Jun LEE
IPC分类号： G06F9/30
CPC分类号： G06F8/40
摘要： An apparatus and method for generating vector code are provided. The apparatus and method generate vector code using scalar-type kernel code, without user's changing a code type or modifying data layout, thereby enhancing user's convenience of use and retaining the portability of OpenCL.
摘要翻译： 提供了一种用于产生矢量码的装置和方法。 该设备和方法使用标量型内核代码生成向量代码，无需用户更改代码类型或修改数据布局，从而提高用户使用方便性并保留OpenCL的可移植性。
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6.发明公开公开(公告)号：US20240103877A1
公开(公告)日：2024-03-28
申请号：US18533041
申请日：2023-12-07
发明人： Jaejin LEE , Jungho PARK , Gangwon JO , Heehoon KIM , Jinpyo KIM
IPC分类号： G06F9/38
CPC分类号： G06F9/3836
摘要： A method for generating an intermediate representation for a program for execution on an accelerator is executed by one or more processors, and includes hooking information on instruction from a program, determining whether the hooked information on instruction is associated with an accelerator, if it is determined that the information on instruction is associated with the accelerator, generating a first intermediate representation for the instruction using information on input and output data and information on instruction included in the instruction, and generating a second intermediate representation for the program for one or more accelerators using the first intermediate representation, and the first intermediate representation and the second intermediate representation include a plurality of data nodes, one or more operation nodes, and a plurality of edges indicating an input and output relationship between the plurality of data nodes and the one or more operation nodes.
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公开(公告)号：US20240126790A1
公开(公告)日：2024-04-18
申请号：US18537683
申请日：2023-12-12
发明人： Jaejin LEE , Jungho PARK , Gangwon JO , Heehoon KIM , Jinpyo KIM
CPC分类号： G06F16/287 , G06F16/23 , G06F16/254
摘要： A method for creating an intermediate representation is performed by one or more processors and includes by an intermediate representation creation unit, extracting, from the program, information on data for input and output and information on operation, by the intermediate representation creation unit, determining the presence or absence of an in-place operation based on the extracted information on data and the extracted information on operation, and by the intermediate representation creation unit, if there is the in-place operation, creating an intermediate representation using the extracted information on data, the extracted information on operation, and a creation rule associated with the in-place operation, in which input data of the in-place operation is data that is replaced with output data after the in-place operation.
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8.发明申请公开(公告)号：US20210064997A1
公开(公告)日：2021-03-04
申请号：US16961073
申请日：2018-11-29
发明人： Jaejin LEE , Jungho PARK
摘要： Embodiments disclosed herein relate to a method for GPU memory management that observes the deep learning of a deep neural network performed by a GPU and reduces the amount of GPU memory used, thereby overcoming limitations attributable to the memory size of the GPU and allowing the more effective performance of the deep learning, and a computing device for performing the same. According to an embodiment, there is disclosed a method for GPU memory management for a deep neural network, the method being performed by a computing device including a GPU and a CPU, the method including: generating a schedule for GPU memory management based on the processing of a unit operation, included in the deep neural network, by the GPU; and moving data required for deep learning of the deep neural network between GPU memory and CPU memory based on the schedule.
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9.发明申请公开(公告)号：US20180203617A1
公开(公告)日：2018-07-19
申请号：US15874322
申请日：2018-01-18
发明人： Jaejin LEE , Gangwon JO
IPC分类号： G06F3/06
摘要： Disclosed herein are a method of transferring data in a parallel system including a main device and at least one accelerator, and a parallel system for performing the method. The method of transferring data in a heterogeneous system including a main device and at least one accelerator includes: turning off a write permission for a first main memory area corresponding to a first accelerator memory area where input data for a computation task is stored; performing the computation task by using the at least one accelerator; and turning off a read permission for a second main memory area corresponding to a second accelerator memory area where output data for the computation task is stored, in the state in which data of the second accelerator memory area has not been transferred to the second main memory area.
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公开(公告)号：US20230290681A1
公开(公告)日：2023-09-14
申请号：US17957473
申请日：2022-09-30
发明人： Taekyung YOON , Youngjun KIM , Hunyoung BARK , Eun-Ok LEE , Jaejin LEE , Dongju CHANG
IPC分类号： H01L21/768 , H01L21/67 , H01L21/3213
CPC分类号： H01L21/76877 , H01L21/76829 , H01L21/67103 , H01L21/3213 , H01L21/76856
摘要： Provided is a method of fabricating a semiconductor device including forming a device isolation layer defining active regions on a substrate and forming gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming a trench crossing the active regions in the substrate, forming a conductive layer filling the trench, and performing a heat treatment process on the conductive layer. The conductive layer includes a nitride of a first metal. Nitrogen atoms in the conductive layer are diffused toward an outer surface and a lower surface of the conductive layer by the heat treatment process.
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