公开(公告)号：US11114459B2

公开(公告)日：2021-09-07

申请号：US16675459

申请日：2019-11-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Hirofumi Tokita ,  Yoshitaka Otsu ,  Fumiaki Toyama ,  Yuki Mizutani

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/788

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.

公开(公告)号：US10290650B1

公开(公告)日：2019-05-14

申请号：US15888714

申请日：2018-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai

IPC: H01L29/76 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524

Abstract: Memory opening fill structures extend through an alternating stack of insulating layers and electrically conductive layers and a combination of an insulating fill material layer and plate electrode portions located over the alternating stack. Each memory opening fill structure includes a memory film, a vertical semiconductor channel laterally surrounded by the memory film, and a tubular electrode portion overlying the alternating stack and contacting a respective one of the plate electrode portions. The insulating fill material layer includes a drain select level isolation structure located between neighboring rows of memory opening fill structures. The plate electrode portions and the tubular electrode portions collectively constitute drain select gate electrodes. The tubular electrode portions are incorporated into a respective memory opening fill structure, and the drain select level isolation structure can be self-aligned to the memory opening fill structures.