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公开(公告)号：US20240111440A1
公开(公告)日：2024-04-04
申请号：US17957424
申请日：2022-09-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0626 , G06F3/0629 , G06F3/0679
摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
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公开(公告)号：US11081443B1
公开(公告)日：2021-08-03
申请号：US16827990
申请日：2020-03-24
发明人： Yuki Mizutani , Masayuki Hiroi , Fumiaki Toyama
IPC分类号： H01L23/522 , H01L27/11519 , H01L27/11524 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L27/11556
摘要： A first vertically alternating sequence of first insulating layers and first spacer material layers and a first-tier retro-stepped dielectric material portion are formed over a substrate. The first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers. A second vertically alternating sequence of second insulating layers and second spacer material layers and a second-tier retro-stepped dielectric material portion are formed over the first vertically alternating sequence and the first-tier retro-stepped dielectric material portion. The second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers. An opening is formed through the second vertically alternating sequence over the first-tier retro-stepped dielectric material portion, and is filled with a dielectric well structure. Contact via structures can be formed through the dielectric well structure and the first-tier retro-stepped dielectric material portion on the first electrically conductive layers.
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3.发明申请THREE DIMENSIONAL MEMORY DEVICE HAVING WELL CONTACT PILLAR AND METHOD OF MAKING THEREOF 审中-公开具有良好接触柱的三维存储器件及其制造方法公开(公告)号：US20160329341A1
公开(公告)日：2016-11-10
申请号：US15216941
申请日：2016-07-22
IPC分类号： H01L27/115 , H01L23/522
CPC分类号： H01L27/11556 , G11C5/02 , G11C16/0408 , G11C16/0483 , G11C2213/71 , H01L23/5226 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.
摘要翻译： 单片三维存储器件包括具有基本上平行于半导体衬底的主表面延伸的第一导电类型的主表面和掺杂阱区的半导体衬底，多个NAND存储器串，基本上垂直于半导体衬底的主表面延伸 所述半导体衬底以及基本上垂直于所述半导体衬底的主表面延伸的多个基本上柱状的支撑构件，每个支撑构件包括围绕导电芯材的电绝缘外部材料，所述导电芯材基本上垂直于所述半导体衬底的主表面延伸 半导体衬底并与掺杂阱区电接触。
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公开(公告)号：US20230367944A1
公开(公告)日：2023-11-16
申请号：US17740705
申请日：2022-05-10
发明人： Yuki Mizutani , Masaaki Higashitani
IPC分类号： G06F30/392 , G06F30/394 , H03K19/0185
CPC分类号： G06F30/392 , G06F30/394 , H03K19/018521
摘要： The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.
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5.发明授权公开(公告)号：US11569259B2
公开(公告)日：2023-01-31
申请号：US16985305
申请日：2020-08-05
发明人： Yuki Mizutani , Masaaki Higashitani
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11565 , H01L23/522 , H01L27/1157
摘要： A memory die can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures vertically extending through the alternating stack. A first layer stack within the alternating stack includes a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces. A second layer stack within the alternating stack includes a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces. The second layer stack can be more distal from the substrate than the first layer stack. Contact via structures can be formed from the top side and the bottom side of the alternating stack.
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公开(公告)号：US09818693B2
公开(公告)日：2017-11-14
申请号：US15269017
申请日：2016-09-19
发明人： Fumiaki Toyama , Hiroyuki Ogawa , Yoko Furihata , James Kai , Yuki Mizutani , Jixin Yu , Jin Liu , Johann Alsmeier
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L27/11582 , H01L27/11573
CPC分类号： H01L27/11582 , H01L21/76802 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L27/0288 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
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公开(公告)号：US09806093B2
公开(公告)日：2017-10-31
申请号：US15269041
申请日：2016-09-19
发明人： Fumiaki Toyama , Yuki Mizutani , Hiroyuki Ogawa
IPC分类号： H01L27/115 , H01L23/528 , H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575
CPC分类号： H01L27/11582 , H01L21/76802 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L27/0288 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
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公开(公告)号：US20240274192A1
公开(公告)日：2024-08-15
申请号：US18358598
申请日：2023-07-25
发明人： Yuki Mizutani
IPC分类号： G11C16/04 , G11C5/06 , H01L25/065 , H10B41/10 , H10B41/20 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/20 , H10B43/35 , H10B43/40 , H10B80/00
CPC分类号： G11C16/0483 , G11C5/063 , H01L25/0657 , H10B41/10 , H10B41/20 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/20 , H10B43/35 , H10B43/40 , H10B80/00 , H01L2225/06506
摘要： Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a second set of bit lines. The second column control circuitry is stacked in an x-direction with the first column control circuitry. The control die also has system control circuitry configured to control the first column control circuitry and the second column control circuitry. The system control circuitry resides in the floorplan beside the stacked column control circuitry to allow for additional routing of electrical connections above the system control circuitry.
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公开(公告)号：US20240215240A1
公开(公告)日：2024-06-27
申请号：US18358584
申请日：2023-07-25
发明人： Ohwon Kwon , Yuki Mizutani , Arka Ganguly , Kou Tei , Yonggang Wu
摘要： Technology is disclosed herein for a memory device having a narrow gap between planes and a method of shrinking the gap between planes. A first and second adjacent planes each has a word line (WL) hookup region at mid-plane. A dummy array region resides between the two planes. The dummy array region may contain a stack of alternating layers of a first insulating material and a second insulating material. There is a first electrical isolation structure between the dummy array region and a stack in the first plane. There is a second electrical isolation structure between the dummy array region and a stack in a second plane. The electrical isolation structures may be formed in narrow trenches. The combination of the dummy array region and the two electrical isolation structures results in a very short gap between the adjacent planes.
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10.发明授权公开(公告)号：US11996153B2
公开(公告)日：2024-05-28
申请号：US17556298
申请日：2021-12-20
发明人： James Kai , Yuki Mizutani , Hisakazu Otoi , Masaaki Higashitani , Hiroyuki Ogawa
IPC分类号： G11C16/08 , G11C8/14 , G11C16/04 , H01L23/48 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： G11C16/0483 , G11C8/14 , H01L23/481 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.
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