公开(公告)号：US20210210466A1

公开(公告)日：2021-07-08

申请号：US17206257

申请日：2021-03-19

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/50 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US20250006635A1

公开(公告)日：2025-01-02

申请号：US18886493

申请日：2024-09-16

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20240274536A1

公开(公告)日：2024-08-15

申请号：US18432890

申请日：2024-02-05

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L27/0924

Abstract: A semiconductor device includes: a substrate; a circuit region provided on the substrate; a first power supply line and a second power supply line, positioned in the circuit region; a first fin and a second fin, each extending in a first direction in the circuit region, in plan view, and protruding from the substrate; a first power supply switching circuit, positioned in the circuit region and including a first transistor formed with the first fin, the first circuit electrically connecting the first and second power supply lines, and the first fin extending in the first power supply switching circuit without cutting; and a second power supply switching circuit, positioned in the circuit region and including a second transistor formed with the second fin, the second circuit electrically connecting the first and second power supply lines, and including a fin-cut part in which the second fin is cut.

公开(公告)号：US20240224492A1

公开(公告)日：2024-07-04

申请号：US18606421

申请日：2024-03-15

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H10B10/00

CPC classification number: H10B10/18

Abstract: A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate, and third and fourth power supply lines provided on a second surface of the substrate. The second power supply line and the third power supply line are connected through vias provided in the substrate. The semiconductor device includes first and second areas arranged to have a third area sandwiched in-between, and a power switch circuit including switch transistors connected between the third and fourth power supply lines.

公开(公告)号：US20220230954A1

公开(公告)日：2022-07-21

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20210210468A1

公开(公告)日：2021-07-08

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka TAKENO ,  Wenzhen WANG ,  Atsushi OKAMOTO

IPC: H01L25/065 ,  H01L27/02

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US20190393206A1

公开(公告)日：2019-12-26

申请号：US16438026

申请日：2019-06-11

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.