公开(公告)号：US20240224491A1

公开(公告)日：2024-07-04

申请号：US18602522

申请日：2024-03-12

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H10B10/00 ,  H01L27/105

CPC classification number: H10B10/18 ,  H01L27/105

Abstract: A semiconductor device includes a peripheral circuit area, a bit cell area, and a separating area positioned between the peripheral circuit area and the bit cell. A first power switch circuit for the peripheral circuit area is connected to a first power supply line, and a second power supply line and a first ground line provided on the substrate; and connects the first power supply line and the second power supply line. The second power switch circuit for the bit cell area is connected to a third power supply line, a fourth power supply line, and a second ground line provided on the substrate; and connects the third power supply line and the fourth power supply line.

公开(公告)号：US20190081029A1

公开(公告)日：2019-03-14

申请号：US16189900

申请日：2018-11-13

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Tomoyasu KITAURA ,  Hirotaka TAKENO

IPC: H01L27/02 ,  H01L23/528 ,  H03K19/00

Abstract: A circuit block including standard cells (1) arranged therein is provided with switch cells (20) capable of switching between electrical connection and disconnection between power supply lines (3) extending in an X-direction and power supply straps (11) extending in a Y-direction. Each of the power supply straps (11) is provided with a single switch cell (20) arranged every M sets of power supply lines (3) (M is an integer of 3 or more). In the Y-direction, the switch cells (20) are arranged at different positions in the power supply straps (11) adjacent to each other, and are arranged at the same position every M power supply straps (11) in the X-direction.

公开(公告)号：US20160099642A1

公开(公告)日：2016-04-07

申请号：US14862240

申请日：2015-09-23

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO

IPC: H02M3/158

CPC classification number: H03K17/162 ,  H03K19/0016 ,  H03K2217/0018 ,  H03K2217/0036

Abstract: A circuit for controlling power supply includes a first switch situated between a first power supply and a first node coupled to a circuit block, a second switch situated between a second power supply having a voltage value different than the first power supply and a second node coupled to a back gate of a transistor of the circuit block, a third switch situated between the first node and the second node, and a control unit configured to place the second switch in an “on” state and the third switch in an “off” state during an “on” state of the first switch, and to place the second switch in an “off” state and the third switch in an “on” state during an “off” state of the first switch.

Abstract translation: 用于控制电源的电路包括位于第一电源和耦合到电路块的第一节点之间的第一开关，位于具有不同于第一电源的电压值的第二电源之间的第二开关和耦合 到位于所述电路块的晶体管的背栅极，位于所述第一节点和所述第二节点之间的第三开关，以及配置为将所述第二开关置于“导通”状态并且所述第三开关处于“断开”状态的控制单元， 在第一开关的“断开”状态期间，将第二开关置于“断开”状态，将第三开关置于“接通”状态。

公开(公告)号：US20250088190A1

公开(公告)日：2025-03-13

申请号：US18957281

申请日：2024-11-22

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H03K19/173 ,  H01L23/495 ,  H01L29/78

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US20240258236A1

公开(公告)日：2024-08-01

申请号：US18608113

申请日：2024-03-18

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226

Abstract: A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate; a third power supply line provided on a second surface of the substrate, and connected to the first power supply line through a via; a fourth power supply line; a first area including the second power supply line, the first ground line, the third power supply line; a second area including the fourth power supply line and the second ground line; a third area positioned between the first area and the second area in plan view; and a power switch circuit including a switch transistor connected between the first power supply line and the second power supply line.

公开(公告)号：US20230120959A1

公开(公告)日：2023-04-20

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Junji IWAHORI

IPC: H03K17/16 ,  H03K17/687

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US20220239297A1

公开(公告)日：2022-07-28

申请号：US17724247

申请日：2022-04-19

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H03K19/173 ,  H01L23/495

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US20160049936A1

公开(公告)日：2016-02-18

申请号：US14797885

申请日：2015-07-13

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO

IPC: H03K19/00 ,  H03K19/0185 ,  H03K17/693

CPC classification number: H03K19/0013 ,  H03K17/693 ,  H03K19/0016 ,  H03K19/018521

Abstract: A semiconductor device includes a first power supply node and a second power supply node having a voltage value higher than the first power supply node. A first switch interrupts a power supplied from the first power supply node to a first circuit node. A second switch interrupts a power supplied from the second power supply node to a second circuit node. A driver drives the second switch by a third switch being driven. The third switch is connected between the second power supply node and the first circuit node. A controller outputs a control signal to drive the first and third switches.

Abstract translation: 半导体器件包括具有比第一电源节点高的电压值的第一电源节点和第二电源节点。 第一开关将从第一电源节点提供的电力中断到第一电路节点。 第二开关将从第二电源节点提供的电力中断到第二电路节点。 驱动器通过被驱动的第三开关驱动第二开关。 第三开关连接在第二电源节点和第一电路节点之间。 控制器输出控制信号以驱动第一和第三开关。

公开(公告)号：US20240387466A1

公开(公告)日：2024-11-21

申请号：US18785950

申请日：2024-07-26

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Wenzhen WANG ,  Atsushi OKAMOTO

IPC: H01L25/065 ,  H01L23/00 ,  H01L27/02

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US20240355786A1

公开(公告)日：2024-10-24

申请号：US18762452

申请日：2024-07-02

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/538 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.