公开(公告)号：US20240224491A1

公开(公告)日：2024-07-04

申请号：US18602522

申请日：2024-03-12

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H10B10/00 ,  H01L27/105

CPC classification number: H10B10/18 ,  H01L27/105

Abstract: A semiconductor device includes a peripheral circuit area, a bit cell area, and a separating area positioned between the peripheral circuit area and the bit cell. A first power switch circuit for the peripheral circuit area is connected to a first power supply line, and a second power supply line and a first ground line provided on the substrate; and connects the first power supply line and the second power supply line. The second power switch circuit for the bit cell area is connected to a third power supply line, a fourth power supply line, and a second ground line provided on the substrate; and connects the third power supply line and the fourth power supply line.

公开(公告)号：US20250056879A1

公开(公告)日：2025-02-13

申请号：US18929016

申请日：2024-10-28

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US20230223381A1

公开(公告)日：2023-07-13

申请号：US18179013

申请日：2023-03-06

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/50 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US20250088190A1

公开(公告)日：2025-03-13

申请号：US18957281

申请日：2024-11-22

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H03K19/173 ,  H01L23/495 ,  H01L29/78

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US20240258236A1

公开(公告)日：2024-08-01

申请号：US18608113

申请日：2024-03-18

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226

Abstract: A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate; a third power supply line provided on a second surface of the substrate, and connected to the first power supply line through a via; a fourth power supply line; a first area including the second power supply line, the first ground line, the third power supply line; a second area including the fourth power supply line and the second ground line; a third area positioned between the first area and the second area in plan view; and a power switch circuit including a switch transistor connected between the first power supply line and the second power supply line.

公开(公告)号：US20220239297A1

公开(公告)日：2022-07-28

申请号：US17724247

申请日：2022-04-19

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Wenzhen WANG

IPC: H03K19/173 ,  H01L23/495

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US20240387466A1

公开(公告)日：2024-11-21

申请号：US18785950

申请日：2024-07-26

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Wenzhen WANG ,  Atsushi OKAMOTO

IPC: H01L25/065 ,  H01L23/00 ,  H01L27/02

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US20240355786A1

公开(公告)日：2024-10-24

申请号：US18762452

申请日：2024-07-02

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/538 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US20240332300A1

公开(公告)日：2024-10-03

申请号：US18744087

申请日：2024-06-14

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US20220231054A1

公开(公告)日：2022-07-21

申请号：US17714683

申请日：2022-04-06

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.