公开(公告)号：US09793321B2

公开(公告)日：2017-10-17

申请号：US14970347

申请日：2015-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.