公开(公告)号：US20220020754A1

公开(公告)日：2022-01-20

申请号：US17491201

申请日：2021-09-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US20210343334A1

公开(公告)日：2021-11-04

申请号：US17375945

申请日：2021-07-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY ,  Nitin CHAWLA

IPC: G11C11/419 ,  H01L27/11

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

公开(公告)号：US20200342940A1

公开(公告)日：2020-10-29

申请号：US16846938

申请日：2020-04-13

Applicant: STMicroelectronics International N.V.

Inventor： Tanmoy ROY ,  Tanuj KUMAR ,  Shishir KUMAR

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C29/44

Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

公开(公告)号：US20200219579A1

公开(公告)日：2020-07-09

申请号：US16702744

申请日：2019-12-04

Applicant: STMicroelectronics International N.V.

Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

IPC: G11C29/38 ,  G11C29/14

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

公开(公告)号：US20190279707A1

公开(公告)日：2019-09-12

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek PATHAK ,  Tanmoy ROY ,  Shishir KUMAR

IPC: G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US20190273484A1

公开(公告)日：2019-09-05

申请号：US16296094

申请日：2019-03-07

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alok Kumar TRIPATHI ,  Amit VERMA ,  Anuj GROVER ,  Deepak Kumar BIHANI ,  Tanmoy ROY ,  Tanuj AGRAWAL

IPC: H03K3/3562 ,  G11C29/00

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.