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    CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT CONDITION IN A MEMORY CIRCUIT
    1.
    发明申请
    CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT CONDITION IN A MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20200243153A1

    公开(公告)日：2020-07-30

    申请号：US16742292

    申请日：2020-01-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir KUMAR ,  Abhishek PATHAK

    IPC: G11C29/38 ,  G11C8/10 ,  G11C29/44

    Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

    CIRCUIT FOR DETECTION OF SINGLE BIT UPSETS IN GENERATION OF INTERNAL CLOCK FOR MEMORY
    2.
    发明申请
    CIRCUIT FOR DETECTION OF SINGLE BIT UPSETS IN GENERATION OF INTERNAL CLOCK FOR MEMORY 审中-公开

    公开(公告)号：US20200099378A1

    公开(公告)日：2020-03-26

    申请号：US16578487

    申请日：2019-09-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir KUMAR ,  Tanuj KUMAR ,  Deepak Kumar BIHANI

    IPC: H03K19/003

    Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.

    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY
    3.
    发明申请
    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY 有权

    公开(公告)号：US20210225453A1

    公开(公告)日：2021-07-22

    申请号：US17222119

    申请日：2021-04-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

    IPC: G11C29/38 ,  G11C29/14

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

    CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT CONDITION IN A MEMORY CIRCUIT
    7.
    发明申请
    CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT CONDITION IN A MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20200342940A1

    公开(公告)日：2020-10-29

    申请号：US16846938

    申请日：2020-04-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Tanmoy ROY ,  Tanuj KUMAR ,  Shishir KUMAR

    IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C29/44

    Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY
    8.
    发明申请
    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY 审中-公开

    公开(公告)号：US20200219579A1

    公开(公告)日：2020-07-09

    申请号：US16702744

    申请日：2019-12-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

    IPC: G11C29/38 ,  G11C29/14

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

    METHOD AND CIRCUIT FOR ADAPTIVE READ-WRITE OPERATION IN SELF-TIMED MEMORY
    9.
    发明申请
    METHOD AND CIRCUIT FOR ADAPTIVE READ-WRITE OPERATION IN SELF-TIMED MEMORY 审中-公开

    公开(公告)号：US20190279707A1

    公开(公告)日：2019-09-12

    申请号：US16351773

    申请日：2019-03-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhishek PATHAK ,  Tanmoy ROY ,  Shishir KUMAR

    IPC: G11C11/412 ,  G11C7/14 ,  G11C11/419

    Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

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