公开(公告)号：US20190354726A1

公开(公告)日：2019-11-21

申请号：US16403275

申请日：2019-05-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Rosalino Critelli ,  Giuseppe Guarnaccia ,  Delphine Le-Goascoz ,  Nicolas Anquet

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/57 ,  G06F21/85 ,  G06F11/10 ,  G06F13/16 ,  G06F3/06

Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.

公开(公告)号：US10419432B2

公开(公告)日：2019-09-17

申请号：US15026588

申请日：2014-10-17

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS S.R.L.

Inventor： Michael Soulie ,  Riccardo Locatelli ,  Valerio Catalano ,  Hajer Ferjani ,  Giuseppe Maruccia ,  Raffaele Guarrasi ,  Giuseppe Guarnaccia

IPC: H04L29/06 ,  G06F12/08 ,  G06F12/06

Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

公开(公告)号：US20190265947A1

公开(公告)日：2019-08-29

申请号：US16256449

申请日：2019-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Marco Rosselli ,  Giuseppe Guarnaccia

IPC: G06F5/14 ,  G06F13/42

Abstract: A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

公开(公告)号：US09660936B2

公开(公告)日：2017-05-23

申请号：US14516300

申请日：2014-10-16

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Riccardo Locatelli ,  Michael Soulie ,  Francesco Giotta ,  Raffaele Guarrasi ,  Giuseppe Guarnaccia

IPC: G06F17/30 ,  H04L12/933 ,  G06F15/173 ,  H04L12/851

CPC classification number: H04L49/109 ,  G06F15/17312 ,  H04L47/24

Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

公开(公告)号：US20160246714A1

公开(公告)日：2016-08-25

申请号：US15026586

申请日：2014-10-15

Applicant: STMICROELECTRONICS (GRENOBLE2) SAS ,  STMICROELECTRONICS S.R.L.

Inventor： Michael Soulie ,  Riccardo Locatelli ,  Valerio Catalano ,  Giuseppe Maruccia ,  Giuseppe Guarnaccia ,  Raffaele Guarrasi

IPC: G06F12/06 ,  G06F17/50 ,  G06F15/78

CPC classification number: G06F12/0607 ,  G06F13/1647 ,  G06F15/7825 ,  G06F17/5077 ,  G06F2212/656

Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

Abstract translation: 一种方法，包括：接收与地址相关联并具有交易目的地的交易，所述地址在存储器的交织区域中; 确定所述交易的多个目的地中的一个，所述交织的存储器区域的不同部分可分别由所述多个目的地可访问; 以及将路由信息与所述事务相关联，所述路由信息与所确定的目的地相关联。