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公开(公告)号：US11494480B2
公开(公告)日：2022-11-08
申请号：US16798062
申请日：2020-02-21
Applicant: PROTON WORLD INTERNATIONAL N.V.
Inventor： Michael Peeters
Abstract: A first circuit is authenticated using a second circuit. A first datum and a second datum are stored in the second circuit. The second datum corresponds to an application of a first function to the first datum and a third datum. The second circuit sends the second datum to the first circuit. The first circuit decrypts the second datum and sends a fourth datum representative of a result of the decrypting to the first second circuit for authentication. The second circuit verifies a correspondence between the first datum and the fourth datum.
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公开(公告)号：US11200936B2
公开(公告)日：2021-12-14
申请号：US16708313
申请日：2019-12-09
Applicant: PROTON WORLD INTERNATIONAL N.V.
Inventor： Michael Peeters
Abstract: A volatile memory circuit includes a first flip-flop, a second flip-flop having a set input coupled to an output of the first flip-flop. Logic circuitry of the memory circuit logically combines an output of the second flip-flop and information representative of the output of the first flip-flop to generate an output of the memory circuit. In response to a read command, the first flip-flop is reset and content of the second flip-flop is output by the circuit.
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公开(公告)号：US20170344310A1
公开(公告)日：2017-11-30
申请号：US15331470
申请日：2016-10-21
Inventor： Michael Peeters , Fabrice Marinet , Jean-Louis Modave , Fabrice Romain
CPC classification number: G06F3/0659 , G06F3/0611 , G06F3/064 , G06F3/0673 , G06F21/52 , G06F21/554 , G06F21/566 , G06F2221/034 , G09C1/00 , H04L9/004 , H04L2209/046 , H04L2209/12
Abstract: An algorithm execution method includes carrying out a first execution of the algorithm by a processing unit, sending at least one first result, which is to be written into a memory, to a memory management circuit, and storing said first result into a first area of the volatile memory. The method also includes carrying out a second execution of the algorithm by the processing unit, sending at least one second result, which is to be written into the memory, to the memory management circuit, and applying, by means of the memory management circuit, a different processing for the at least one second result in the second execution than was applied for the at least one first results in the first execution.
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公开(公告)号：US12189754B2
公开(公告)日：2025-01-07
申请号：US17654167
申请日：2022-03-09
Applicant: Proton World International N.V.
Inventor： Michael Peeters
Abstract: The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.
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公开(公告)号：US20240281384A1
公开(公告)日：2024-08-22
申请号：US18646226
申请日：2024-04-25
Applicant: Proton World International N.V
Inventor： Michael Peeters
CPC classification number: G06F12/1408 , G06F12/0238 , G06F12/1441 , G06F12/1458
Abstract: The present disclosure relates to secure storage, in a non-volatile memory, of initial data encrypted using a second data, including selecting a pointer aimed at an initial address of a memory cell of an initial part of the non-volatile memory, and encrypting the pointer using the second data; and-storing the encrypted pointer in the non-volatile memory.
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Patent Agency Ranking
公开(公告)号：US11651064B2
公开(公告)日：2023-05-16
申请号：US16832966
申请日：2020-03-27
Inventor： Michael Peeters , Fabrice Marinet
CPC classification number: G06F21/44 , G06F7/57 , G06F9/3818
Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.
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公开(公告)号：US20220327194A1
公开(公告)日：2022-10-13
申请号：US17654167
申请日：2022-03-09
Applicant: Proton World International N.V.
Inventor： Michael Peeters
IPC: G06F21/44
Abstract: The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.
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公开(公告)号：US11003595B2
公开(公告)日：2021-05-11
申请号：US16841403
申请日：2020-04-06
Inventor： Michael Peeters , Fabrice Marinet , Jean-Louis Modave
Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
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公开(公告)号：US10162540B2
公开(公告)日：2018-12-25
申请号：US15380509
申请日：2016-12-15
Applicant: Proton World International N.V.
Inventor： Michel Dawirs , Jean-Louis Modave , Michael Peeters , Guillaume Docquier
Abstract: A flash memory is divided into pages defining an erase granularity of the flash memory. A count value is written into page metadata. Each page is divided into frames. Each frame contains at least one data block and at least two frame metadata words including a first frame metadata word to store a block identifier. A current page is opened by incrementing the count value and writing the incremented count value into the at least one first page metadata word. The current page has its at least one first page metadata word containing a highest count value of the counter of the number of written pages. A logic data block is written into a selected frame and a block identifier of the logic data block is written into the first frame metadata word of the selected frame.
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公开(公告)号：US20170336996A1
公开(公告)日：2017-11-23
申请号：US15380509
申请日：2016-12-15
Applicant: Proton World International N.V.
Inventor： Michel Dawirs , Jean-Louis Modave , Michael Peeters , Guillaume Docquier
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1004 , G06F12/0246 , G06F2212/1036 , G06F2212/7204 , G06F2212/7207 , G06F2212/7209
Abstract: A flash memory management method, including: the data to be stored are organized in logic blocks; the memory is divided into pages; each page is divided into frames, each frame being capable of containing at least one data block and at least two frame metadata words; each page comprises at least one page metadata word which contains, when a page is written, a value of a counter of the number of written pages; a writing of a logic block into the memory goes along with a programming of a first frame metadata word with an identifier of this logic block; and the page into which the writing is to be performed is selected as being that having its first metadata word containing the maximum value of the counter of written pages from among all pages.
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