公开(公告)号：US20250052788A1

公开(公告)日：2025-02-13

申请号：US18788967

申请日：2024-07-30

Applicant: STMicroelectronics International N.V.

Inventor： Deepak Kumar ARORA ,  Tanisha GUPTA ,  Shubham JAIN ,  Anuj GROVER

IPC: G01R13/02 ,  G11C27/02

Abstract: Systems, apparatuses, and methods for an on chip dynamic IR oscilloscope are provided. An oscilloscope circuitry may comprise sensor circuitry, voltage generator circuitry, finite state machine, and latch circuitry. The sensor circuitry may include digital logic circuitry, sample and hold circuitry, and sense amplifier circuitry. The voltage generator circuitry may include a voltage generator, analog buffers, switches, and high speed buffer. The finite state machine may control the sensor circuitry to sample a voltage waveform and the voltage generator circuitry to generate a reference voltage that may change over time. The sensing amplifier circuitry may compare the samples to the reference voltage to generate flags when a sample exceeds a reference voltage. The flags may be used to stored the voltages associated with the flags, which may be used to redraw the waveform sampled.

公开(公告)号：US20230350483A1

公开(公告)日：2023-11-02

申请号：US18338950

申请日：2023-06-21

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G05F3/24 ,  G11C11/413 ,  G06F1/3234 ,  G06F1/3287 ,  G06F15/78

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20220238150A1

公开(公告)日：2022-07-28

申请号：US17721956

申请日：2022-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US20210343334A1

公开(公告)日：2021-11-04

申请号：US17375945

申请日：2021-07-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY ,  Nitin CHAWLA

IPC: G11C11/419 ,  H01L27/11

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

公开(公告)号：US20190273484A1

公开(公告)日：2019-09-05

申请号：US16296094

申请日：2019-03-07

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alok Kumar TRIPATHI ,  Amit VERMA ,  Anuj GROVER ,  Deepak Kumar BIHANI ,  Tanmoy ROY ,  Tanuj AGRAWAL

IPC: H03K3/3562 ,  G11C29/00

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.