公开(公告)号：US20230350483A1

公开(公告)日：2023-11-02

申请号：US18338950

申请日：2023-06-21

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G05F3/24 ,  G11C11/413 ,  G06F1/3234 ,  G06F1/3287 ,  G06F15/78

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20210181828A1

公开(公告)日：2021-06-17

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G06F1/3234 ,  G11C11/413 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20250078883A1

公开(公告)日：2025-03-06

申请号：US18951392

申请日：2024-11-18

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

公开(公告)号：US20240395319A1

公开(公告)日：2024-11-28

申请号：US18791901

申请日：2024-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US20230410862A1

公开(公告)日：2023-12-21

申请号：US18136491

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/16 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/16 ,  G11C8/08 ,  G11C7/12

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

公开(公告)号：US20250054529A1

公开(公告)日：2025-02-13

申请号：US18930022

申请日：2024-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Promod KUMAR ,  Harsh RAWAT

IPC: G11C8/20 ,  G11C11/418

Abstract: A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.

公开(公告)号：US20240143239A1

公开(公告)日：2024-05-02

申请号：US18379373

申请日：2023-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Nitin CHAWLA

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0655

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

公开(公告)号：US20230410892A1

公开(公告)日：2023-12-21

申请号：US18137261

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4085

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

公开(公告)号：US20230386564A1

公开(公告)日：2023-11-30

申请号：US18137159

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Nitin CHAWLA ,  Promod KUMAR ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

公开(公告)号：US20230012567A1

公开(公告)日：2023-01-19

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.