公开(公告)号：US20210081773A1

公开(公告)日：2021-03-18

申请号：US17023144

申请日：2020-09-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Manuj AYODHYAWASI ,  Thomas BOESCH ,  Surinder Pal SINGH

IPC: G06N3/063 ,  G06F1/08 ,  G06F1/324 ,  G06F9/50 ,  G06N3/08 ,  G06F1/3228 ,  G06F1/3296

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：US20230350483A1

公开(公告)日：2023-11-02

申请号：US18338950

申请日：2023-06-21

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G05F3/24 ,  G11C11/413 ,  G06F1/3234 ,  G06F1/3287 ,  G06F15/78

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20230004354A1

公开(公告)日：2023-01-05

申请号：US17940654

申请日：2022-09-08

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin CHAWLA ,  Tanmoy ROY ,  Anuj GROVER ,  Giuseppe DESOLI

IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：US20210181828A1

公开(公告)日：2021-06-17

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G06F1/3234 ,  G11C11/413 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20210072894A1

公开(公告)日：2021-03-11

申请号：US17012501

申请日：2020-09-04

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20180189229A1

公开(公告)日：2018-07-05

申请号：US15423272

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe DESOLI ,  Thomas BOESCH ,  Nitin CHAWLA ,  Surinder Pal SINGH ,  Elio GUIDETTI ,  Fabio Giuseppe DE AMBROGGI ,  Tommaso MAJO ,  Paolo Sergio ZAMBOTTI

IPC: G06F15/78 ,  G06N3/04 ,  G06F13/40

Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

公开(公告)号：US20240045589A1

公开(公告)日：2024-02-08

申请号：US18488581

申请日：2023-10-17

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20220269410A1

公开(公告)日：2022-08-25

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20210241806A1

公开(公告)日：2021-08-05

申请号：US17158875

申请日：2021-01-26

Applicant: STMicroelectronics International N.V. ,  STMICROELECTRONICS S.r.l.

Inventor： Nitin CHAWLA ,  Thomas BOESCH ,  Anuj Grover ,  Surinder Pal SINGH ,  Giuseppe DESOLI

IPC: G11C8/04 ,  G06N3/02

Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

公开(公告)号：US20250078883A1

公开(公告)日：2025-03-06

申请号：US18951392

申请日：2024-11-18

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.