Abstract:
A driver device for driving a DC motor using PWM modulated drive signals includes comparator circuits for producing digitalized Back-EMF signals having first and second values as a function of the Back-EMF signals being above or below a respective threshold, and an inverter for driving the PWM modulated drive signals in a phased relationship with the digitalized Back-EMF signals. The driver device also includes controller circuits configured for controlling the respective threshold by minimizing the error between a time measured between two consecutive opposed edges of the digitalized Back-EMF signal and half a time measured between two consecutive homologous edges of the digitalized Back-EMF signal.
Abstract:
Electric circuit for estimating the angular position of a rotor of an electric motor, including: a sensing module configured to receive at least one electric signal representative of a drive current of the electric motor and to generate a measurement signal indicative of a switching of the at least one electric signal and a switching index indicative of the type of switching, rising or falling, of the at least one electric signal; and a computing module configured to supply, from the measurement signal and switching index a position signal representative of an angular position of the electric motor rotor.
Abstract:
A method for controlling a BLDC motor includes controlling the rotational speed or position of the BLDC motor based on a position of the rotor of the motor. The BLDC motor is driven by a three-phase inverter. A PWM signal is generated for three PWM phases, each including a pair of complementary signals with dead-time and having a duty cycle based on the current position of the rotor. The complementary signals are supplied to a respective high side and low side switch of each of three arms of the three-phase inverter, and a zero-crossing time measurement is performed on each of the back electromotive forces. Corresponding signals are obtained indicating the zero-crossing times. Trigger signals are generated, and the occurrence of a time interval corresponding to the dead time in the respective PWM phase is identified. The zero-crossing time measurement is performed during the occurrence of the dead-time.
Abstract:
A method for controlling a BLDC motor includes controlling the rotational speed or position of the BLDC motor based on a position of the rotor of the motor. The BLDC motor is driven by a three-phase inverter. A PWM signal is generated for three PWM phases, each including a pair of complementary signals with dead-time and having a duty cycle based on the current position of the rotor. The complementary signals are supplied to a respective high side and low side switch of each of three arms of the three-phase inverter, and a zero-crossing time measurement is performed on each of the back electromotive forces. Corresponding signals are obtained indicating the zero-crossing times. Trigger signals are generated, and the occurrence of a time interval corresponding to the dead time in the respective PWM phase is identified. The zero-crossing time measurement is performed during the occurrence of the dead-time.
Abstract:
Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.
Abstract:
A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.
Abstract:
Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.
Abstract:
A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.