Abstract:
A half-bridge driver circuit includes an amplifier configured to generate a measurement signal indicative of a current flowing through a shunt resistor. A processing circuit is configured to selectively acquire a sample of the measurement signal in response to a trigger signal. A synchronization circuit is configured to determine a first value indicative of the switch-on duration of a high side control signal, determine a second value indicative of the switching period of the high side control signal, compute a third value based on the first and second values, generate a third signal based on the third value when the next switching period of the high side control signal starts, start a second counter in response to the third signal, compare the count value of the second counter with a reference value to generate a fourth signal, and generate the trigger signal as a function of the fourth signal.
Abstract:
Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.
Abstract:
A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.
Abstract:
In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.
Abstract:
A half-bridge driver circuit includes an amplifier configured to generate a measurement signal indicative of a current flowing through a shunt resistor. A processing circuit is configured to selectively acquire a sample of the measurement signal in response to a trigger signal. A synchronization circuit is configured to determine a first value indicative of the switch-on duration of a high side control signal, determine a second value indicative of the switching period of the high side control signal, compute a third value based on the first and second values, generate a third signal based on the third value when the next switching period of the high side control signal starts, start a second counter in response to the third signal, compare the count value of the second counter with a reference value to generate a fourth signal, and generate the trigger signal as a function of the fourth signal.
Abstract:
In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.
Abstract:
Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.
Abstract:
Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.
Abstract:
Electric circuit for estimating the angular position of a rotor of an electric motor, including: a sensing module configured to receive at least one electric signal representative of a drive current of the electric motor and to generate a measurement signal indicative of a switching of the at least one electric signal and a switching index indicative of the type of switching, rising or falling, of the at least one electric signal; and a computing module configured to supply, from the measurement signal and switching index a position signal representative of an angular position of the electric motor rotor.
Abstract:
A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.