公开(公告)号：US09012259B2

公开(公告)日：2015-04-21

申请号：US14157097

申请日：2014-01-16

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Foncellino ,  Giovanna Salzillo ,  Valeria Casuscelli ,  Luigi Giuseppe Occhipinti

IPC: H01L51/40 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L51/0545 ,  H01L51/0005 ,  H01L51/0023 ,  H01L51/0525

Abstract: The present disclosure describes a process strategy for forming bottom gate/bottom contact organic TFTs in CMOS technology by using a hybrid deposition/patterning regime. To this end, gate electrodes, gate dielectric materials and drain and source electrodes are formed on the basis of lithography processes, while the organic semiconductor materials are provided as the last layers by using a spatially selective printing process.

Abstract translation: 本公开描述了通过使用混合沉积/图案化方案在CMOS技术中形成底栅/底接触有机TFT的工艺策略。 为此，基于光刻工艺形成栅极电极，栅极电介质材料和漏极和源极电极，而通过使用空间选择性印刷工艺将有机半导体材料提供为最后层。

公开(公告)号：US20140087552A1

公开(公告)日：2014-03-27

申请号：US14032067

申请日：2013-09-19

Applicant: STMicroelectronics S.r.l.

Inventor： Vincenza Di Palma ,  Andrea Di Matteo ,  Luigi Giuseppe Occhipinti

IPC: H01L21/768 ,  H01L21/321

CPC classification number: H01L21/76805 ,  H01L21/32115 ,  H01L51/0018 ,  H01L51/0023 ,  H01L51/0516

Abstract: The present disclosure relates to microstructure devices, in which a conductive pattern is formed on the basis of a conductive polymer material. In order to avoid the deposition and processing of the sacrificial materials and reduce a negative influence of the lithography process on sensitive conductive polymer materials a one-layer patterning sequence is proposed, in which a trench pattern is formed in a dielectric material that is subsequently filled with the conductive polymer material.

Abstract translation: 本公开涉及其中基于导电聚合物材料形成导电图案的微结构器件。 为了避免牺牲材料的沉积和处理并减少光刻工艺对敏感导电聚合物材料的负面影响，提出了一种单层图案化顺序，其中沟槽图案形成在随后填充的电介质材料中 与导电聚合物材料。