-
公开(公告)号：US12073860B2
公开(公告)日：2024-08-27
申请号：US18191639
申请日：2023-03-28
Applicant: STMicroelectronics S.r.l.
Inventor： Dario Livornesi , Alessio Emanuele Vergani , Paolo Pulici , Francesco Piscitelli , Enrico Mammei , Mojtaba Mohammadi Abdevand , Piero Malcovati , Edoardo Bonizzoni
CPC classification number: G11B5/6029 , G11B5/607 , H03F1/0261
Abstract: According to an embodiment, a circuit includes a biasing and a low-frequency recovery circuit. The biasing circuit includes a voltage digital to analog converter (V-DAC), a differential difference amplifier coupled to the V-DAC, a common-mode feedback (CMFB) amplifier coupled to the differential difference amplifier, and a first pair of transistors arranged as a high-impedance structure and coupled to the differential difference amplifier and the CMFB amplifier. The low-frequency recovery circuit includes a current digital to analog converter (C-DAC), a second pair of transistors arranged as a high-impedance structure and coupled to the first pair of transistors, a pair of resistors having a resistance value equal to half a resistance of the resistive sensor, the pair of resistors arranged between the second pair of transistors and coupled to the C-DAC, and a gain circuit coupled to shared nodes between the second pair of transistors and the pair of resistors.
-
公开(公告)号：US11894810B2
公开(公告)日：2024-02-06
申请号：US17952574
申请日：2022-09-26
Applicant: STMicroelectronics S.r.l.
Inventor： Mattia Fausto Moretti , Paolo Pulici , Alessio Facen
CPC classification number: H03F1/26 , H03F3/45192
Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
-
Patent Agency Ranking
公开(公告)号：US20230314117A1
公开(公告)日：2023-10-05
申请号：US18191689
申请日：2023-03-28
Applicant: STMicroelectronics S.r.l.
Inventor： Dario Livornesi , Mattia Fausto Moretti , Paolo Pulici , Alessio Emanuele Vergani , Alessio Facen , Michele Bartolini , Roberto Faravelli , Francesco Piscitelli
Abstract: According to an embodiment, a circuit includes a core and low-frequency recovery circuits. The core circuit is configured to bias a resistive sensor used to measure a fly height of a hard disk drive. The core circuit is additionally configured to amplify a high-frequency component of a sensing signal of the resistive sensor, the sensing signal indicating the fly height. The low-frequency recovery circuit is configured to amplify the sensing signal's low-frequency component.
-
公开(公告)号：US11756582B1
公开(公告)日：2023-09-12
申请号：US17742202
申请日：2022-05-11
Applicant: STMicroelectronics, Inc. , STMicroelectronics S.r.l.
Inventor： Paolo Pulici , Dennis Hogg , Michele Bartolini , Enrico Sentieri , Enrico Mammei
CPC classification number: G11B5/6017 , G11B21/106
Abstract: A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.
-
公开(公告)号：US11489496B2
公开(公告)日：2022-11-01
申请号：US17172676
申请日：2021-02-10
Applicant: STMicroelectronics S.r.l.
Inventor： Mattia Fausto Moretti , Paolo Pulici , Alessio Facen
Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
-
16.发明授权公开(公告)号：US09712060B2
公开(公告)日：2017-07-18
申请号：US15087082
申请日：2016-03-31
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Paolo Pulici , Massimo Mazzucco
CPC classification number: H02M3/1584 , G05F1/46 , H02M1/08 , H02M3/156 , H02M2001/0025 , H02M2001/008
Abstract: A method manages hysteretic DC-DC buck converters each including a hysteretic comparator operating according to a respective hysteresis window. The method includes, in a given converter, verifying if a respective feedback voltage reaches a lower threshold in order to enter a switch-on period of the converter, The method comprises: while the verifying indicates that the lower threshold is not reached, detecting if another converter has entered a respective switch on period and, in the affirmative, entering a hysteresis voltage adjustment procedure, include increasing by a given amount the amplitude of the hysteresis window of the given converter by reducing the lower threshold of the hysteresis window.
-
17.发明申请公开(公告)号：US20170085180A1
公开(公告)日：2017-03-23
申请号：US15087082
申请日：2016-03-31
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Paolo Pulici , Massimo Mazzucco
CPC classification number: H02M3/1584 , G05F1/46 , H02M1/08 , H02M3/156 , H02M2001/0025 , H02M2001/008
Abstract: A method manages hysteretic DC-DC buck converters each including a hysteretic comparator operating according to a respective hysteresis window. The method includes, in a given converter, verifying if a respective feedback voltage reaches a lower threshold in order to enter a switch-on period of the converter, The method comprises: while the verifying indicates that the lower threshold is not reached, detecting if another converter has entered a respective switch on period and, in the affirmative, entering a hysteresis voltage adjustment procedure, include increasing by a given amount the amplitude of the hysteresis window of the given converter by reducing the lower threshold of the hysteresis window.
-
-
-
-
-
-
Search Results
17
records
(took 0.025 seconds)
