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公开(公告)号：US11756582B1
公开(公告)日：2023-09-12
申请号：US17742202
申请日：2022-05-11
发明人： Paolo Pulici , Dennis Hogg , Michele Bartolini , Enrico Sentieri , Enrico Mammei
CPC分类号： G11B5/6017 , G11B21/106
摘要： A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.
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公开(公告)号：US20230386514A1
公开(公告)日：2023-11-30
申请号：US18191639
申请日：2023-03-28
发明人： Dario Livornesi , Alessio Emanuele Vergani , Paolo Pulici , Francesco Piscitelli , Enrico Mammei , Mojtaba Mohammadi Abdevand , Piero Malcovati , Edoardo Bonizzoni
CPC分类号： G11B5/6029 , G11B5/607 , H03F1/0261
摘要： According to an embodiment, a circuit includes a biasing and a low-frequency recovery circuit. The biasing circuit includes a voltage digital to analog converter (V-DAC), a differential difference amplifier coupled to the V-DAC, a common-mode feedback (CMFB) amplifier coupled to the differential difference amplifier, and a first pair of transistors arranged as a high-impedance structure and coupled to the differential difference amplifier and the CMFB amplifier. The low-frequency recovery circuit includes a current digital to analog converter (C-DAC), a second pair of transistors arranged as a high-impedance structure and coupled to the first pair of transistors, a pair of resistors having a resistance value equal to half a resistance of the resistive sensor, the pair of resistors arranged between the second pair of transistors and coupled to the C-DAC, and a gain circuit coupled to shared nodes between the second pair of transistors and the pair of resistors.
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公开(公告)号：US20220413531A1
公开(公告)日：2022-12-29
申请号：US17362532
申请日：2021-06-29
摘要： In an embodiment, a linear voltage regulator includes: an output transistor having a first current path terminal configured to be coupled to a load, and a second current path terminal coupled to a first supply terminal, where the output transistor is configured to provide, at the first current path terminal, a regulated output voltage; a voltage source circuit configured to provide, in an open loop manner, a first voltage to a control terminal of the output transistor; and a feedback loop coupled between the first current path terminal of the output transistor and the control terminal of the output transistor, the feedback loop including a sense transistor having a first current path terminal coupled to the first current path terminal of the output transistor.
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4.发明授权Through via structure including a conductive portion and aligned solder portion 有权通孔结构包括导电部分和对准的焊接部分公开(公告)号：US08928123B2
公开(公告)日：2015-01-06
申请号：US14291749
申请日：2014-05-30
IPC分类号： H01L29/40 , H01L23/00 , H01L23/498
CPC分类号： H01L24/06 , H01L21/76898 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/10126 , H01L2224/13009 , H01L2224/131 , H01L2224/13111 , H01L2224/13186 , H01L2224/16 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/04941 , H01L2224/13099 , H01L2924/00
摘要： A substrate has a first surface and a second surface opposed to each other. A blind hole is formed in the substrate extending from the first surface at a location for each through via. Each blind hole is filled with a conductive filler; a deepest part of each filler forming a bump portion made of a solder material. Part of the substrate extending from the second surface is removed to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding solder bump.
摘要翻译： 衬底具有彼此相对的第一表面和第二表面。 在每个通孔的位置处，从第一表面延伸的基板上形成盲孔。 每个盲孔填充有导电填料; 每个填料的最深部分形成由焊料材料制成的凸起部分。 移除从第二表面延伸的基板的一部分，以至少凸起部分从基板突出。 每个填料的非突出部分限定相应的通孔，凸起部分限定相应的焊料凸块。
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公开(公告)号：US20240177732A1
公开(公告)日：2024-05-30
申请号：US18432776
申请日：2024-02-05
发明人： Marco Mazzini , Marco Ciuffolini , Enrico Mammei , Paolo Pulici
CPC分类号： G11B5/012 , G05F1/56 , H05B3/22 , G11B2005/0021
摘要： In accordance with an embodiment, a circuit is configured to vary an intensity of a drive current of a resistive heater element based on the digital control signal. The circuit includes and output circuit configured to control a respective slew rate and an electric energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.
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公开(公告)号：US10965254B2
公开(公告)日：2021-03-30
申请号：US16392009
申请日：2019-04-23
摘要： A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
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公开(公告)号：US11720128B2
公开(公告)日：2023-08-08
申请号：US17362532
申请日：2021-06-29
摘要： In an embodiment, a linear voltage regulator includes: an output transistor having a first current path terminal configured to be coupled to a load, and a second current path terminal coupled to a first supply terminal, where the output transistor is configured to provide, at the first current path terminal, a regulated output voltage; a voltage source circuit configured to provide, in an open loop manner, a first voltage to a control terminal of the output transistor; and a feedback loop coupled between the first current path terminal of the output transistor and the control terminal of the output transistor, the feedback loop including a sense transistor having a first current path terminal coupled to the first current path terminal of the output transistor.
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公开(公告)号：US20230009311A1
公开(公告)日：2023-01-12
申请号：US17952574
申请日：2022-09-26
摘要： A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
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公开(公告)号：US20140264852A1
公开(公告)日：2014-09-18
申请号：US14291749
申请日：2014-05-30
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/06 , H01L21/76898 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/10126 , H01L2224/13009 , H01L2224/131 , H01L2224/13111 , H01L2224/13186 , H01L2224/16 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/04941 , H01L2224/13099 , H01L2924/00
摘要： A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.
摘要翻译： 一种用于制造具有彼此相对的第一表面和第二表面的基板中的通孔的焊料凸块的方法。 该方法包括以下步骤：从每个通孔的第一表面形成在基板中延伸的盲孔，并用导电填料填充每个盲孔; 每个填料的最深部分包括由焊料材料制成的凸起部分。 所述方法还包括从所述第二表面移除所述基板的一部分以至少具有从所述基板突出的凸起部的步骤。 每个填料的非突出部分限定相应的通孔，凸起部分限定相应的凸块。
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公开(公告)号：US11855588B2
公开(公告)日：2023-12-26
申请号：US17581334
申请日：2022-01-21
发明人： Edoardo Marino , Alessio Vallese , Alessio Facen , Enrico Mammei , Paolo Pulici
CPC分类号： H03F1/3211 , H03F3/45179 , H03F3/45479 , H03F3/4508 , H03F3/45085
摘要： In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.
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