Abstract:
A display panel driving apparatus includes a load controlling circuit, a data driver and a gate driver. The load controlling circuit is connected to a control line transferring a recovery timing control signal for controlling recovery of a clock signal from a display signal including image data and the clock signal, and is configured to control a load of the control line according to a glitch level of the recovery timing control signal. The data driver is configured to receive the display signal, receive the recovery timing control signal through a connection to the control line, recover the clock signal from the display signal according to the recovery timing control signal, and output a data signal based on the image data to a data line of a display panel.
Abstract:
A display apparatus includes a display panel including a plurality of data lines arranged in a first direction, where the data line extends substantially in a second direction, and a plurality of pixels electrically connected to the data lines, and a data driver configured to output a first data voltage and a second data voltage to the data lines and configured to control the number of the data lines which receives the first data voltage and the number of the data lines which receive the second data voltage, where the first data voltage has a positive polarity during a first frame and a negative polarity during a second frame, and the second data voltage has the negative polarity during the first frame and the positive polarity during the second frame.
Abstract:
A display panel driving apparatus is disclosed. In one aspect the apparatus includes a gate driving part and a data driving part. The gate driving part is configured to increase a gate signal applied to a gate line of a display panel from an OFF voltage to a ON voltage, in response to an activation of a gate clock signal. It is also configured to decrease the gate signal from the ON voltage to a kickback compensation voltage between the OFF voltage and the ON voltage through a plurality of steps in response to an activation of a kickback compensation signal. The data driving part is configured to apply a data signal to a data line of the display panel. Therefore, a data-charging rate may be increased, and thus a display quality of the display apparatus may be increased.
Abstract:
A display panel driving apparatus includes a load controlling circuit, a data driver and a gate driver. The load controlling circuit is connected to a control line transferring a recovery timing control signal for controlling recovery of a clock signal from a display signal including image data and the clock signal, and is configured to control a load of the control line according to a glitch level of the recovery timing control signal. The data driver is configured to receive the display signal, receive the recovery timing control signal through a connection to the control line, recover the clock signal from the display signal according to the recovery timing control signal, and output a data signal based on the image data to a data line of a display panel.
Abstract:
A method of driving a display panel is provided. The method includes displaying a first image on at least one odd-numbered horizontal line of the display panel along a first direction and a second direction during a first period of a frame period and displaying a second image on at least one even-numbered horizontal line of the display panel along the first direction and second direction during a second period of the frame period.
Abstract:
A display apparatus includes a display panel, a memory, a bit-data convertor, a switch, and a gate driver. The display panel includes pixels. Each pixel is connected to one of the data lines and one of the gate lines. The memory stores a plurality of image data corresponding to a frame period. The bit-data convertor determines a plurality of bit data. Each of the bit data corresponds to a degree of change between adjacent image data among the plurality of image data, obtains a sum of the bit data, and outputs the sum of the bit data as a total count bit data value. The switch outputs a first pulse control signal corresponding to the total count bit data value. The gate driver generates a gate signal based on the first pulse control signal, and to output the gate signal to one of the gate lines.
Abstract:
A method of driving a display panel includes: selectively providing a resistance using resistor parts in response to address signals, where the resistor parts have resistances, respectively; and outputting common voltages to the display panel based on the selectively provided resistance.
Abstract:
A method of driving a display panel is provided. The method includes displaying a first image on at least one odd-numbered horizontal line of the display panel along a first direction and a second direction during a first period of a frame period and displaying a second image on at least one even-numbered horizontal line of the display panel along the first direction and second direction during a second period of the frame period.
Abstract:
A method of driving a display panel includes: selectively providing a resistance using resistor parts in response to address signals, where the resistor parts have resistances, respectively; and outputting common voltages to the display panel based on the selectively provided resistance.
Abstract:
A liquid crystal display device, including a display panel including data lines and gate lines intersecting the data lines, a gate driver configured to sequentially apply a scan signal to the gate lines, a data driver configured to apply data voltages corresponding to each gate lines to the data lines, a timing controller configured to control the gate driver and the data driver, a power source supply circuit configured to supply a positive power source and a negative power source, a common voltage feedback circuit configured to receive the positive power source and the negative power source from the power source supply circuit, receive a reference voltage and a common voltage from the display panel, and output an amplified feedback signal corresponding to a voltage level difference between the reference voltage and the common voltage.