Abstract:
A liquid crystal display, including: a liquid crystal panel; and a visual inspection unit positioned in an outer region of the liquid crystal panel and transferring a test signal to the liquid crystal panel, in which the visual inspection unit includes: a test pad to which a test signal is applied; a first test line connected to the test pad; and a second test line connected to the test pad through a bridge line.
Abstract:
Provided is a liquid crystal display including: a first substrate; a gate line, a data line, and a common voltage line formed on the first substrate; a first passivation layer formed on the gate line, the data line, and the common voltage line; and a pixel electrode and a common electrode formed on the first passivation layer and overlapping each other with a second passivation layer therebetween, and the common electrode is connected to the common voltage line through a common contact hole, and the common contact hole is disposed for every two or more dots.
Abstract:
A liquid crystal display device for improving picture quality includes a common electrode formed on a first substrate, gate lines and data lines formed on a second substrate bonded to the first substrate by a sealing member with liquid crystals disposed therebetween, thin film transistors connected to the gate lines and to the data lines, pixel electrodes formed in subpixel regions, each pixel electrode having a long side in a direction of the gate lines and having a short side in a direction of the data lines fanout lines for supplying a driving signals from the driving chips to the data lines, first conductive spacers formed between the fanout lines connected to different driving chips, for supplying a common voltage to the common electrode, and second conductive spacers formed between the fanout lines connected to the same driving chip, for supplying the common voltage to the common electrode.
Abstract:
A liquid-crystal display device, including: a first data line and a second data line each lengthwise extended in a first direction and spaced apart from each other, a gate line lengthwise extended in a second direction different from the first direction, the gate line defining: a first region thereof overlapping the first data line, a second region thereof overlapping the second data line and a third region thereof extended between the first region and the second region, and a pixel including a switching element, a first electrode of the switching element being connected to the first data line and a second electrode of the switching element overlapping each of the first to third regions. In the first direction, a width of the third region is smaller than a width of each of the first and second regions.
Abstract:
A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.
Abstract:
Provided is a liquid crystal display including a plurality of pixels disposed in a matrix of pixel rows and pixel columns, the liquid crystal display including: a plurality of gate lines formed on a first substrate and disposed two between every pixel row; a plurality of data lines formed on the first substrate and disposed one between every two adjacent pixel columns; a common voltage line formed on the first substrate and extending in a pixel row direction along a vertical center of the pixel; and a plurality of pixel electrodes and common electrodes formed on the first substrate and overlapping with each other with an insulating layer therebetween, each pixel electrode positioned in a pixel, and in which two pixel electrodes in the two pixel columns disposed between two adjacent data lines among the plurality of data lines are both connected to any one of the two data lines.
Abstract:
A thin film transistor array panel and a display device including the same are disclosed. In one aspect, the thin film transistor array panel includes a plurality of dots located in a display area, each of the plurality of dots including a plurality of pixels, and a plurality of data lines applying data voltages to the plurality of pixels. The thin film transistor array panel also includes a plurality of first dummy data lines located in a first peripheral area of a peripheral area around the display area, the plurality of first dummy data lines are adjacent to a first edge of the display area. The thin film transistor array panel further includes plurality of first data lines applying data voltages to the pixels included in a first dot adjacent to the first edge and are respectively connected to the plurality of first dummy data lines.
Abstract:
A thin film transistor array panel and a display device including the same are disclosed. In one aspect, the thin film transistor array panel includes a plurality of dots located in a display area, each of the plurality of dots including a plurality of pixels, and a plurality of data lines applying data voltages to the plurality of pixels. The thin film transistor array panel also includes a plurality of first dummy data lines located in a first peripheral area of a peripheral area around the display area, the plurality of first dummy data lines are adjacent to a first edge of the display area. The thin film transistor array panel further includes plurality of first data lines applying data voltages to the pixels included in a first dot adjacent to the first edge and are respectively connected to the plurality of first dummy data lines.
Abstract:
A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.