公开(公告)号：US20230140959A1

公开(公告)日：2023-05-11

申请号：US18149206

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk Yu

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/08 ,  G11C16/04

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L24/05 ,  H01L24/08 ,  G11C16/08 ,  G11C16/0483 ,  H01L2924/14511 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US20220156014A1

公开(公告)日：2022-05-19

申请号：US17665926

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20210366825A1

公开(公告)日：2021-11-25

申请号：US17212222

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongha SHIN ,  Jeawon JEONG ,  Bongsoon LIM

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.

公开(公告)号：US20210202457A1

公开(公告)日：2021-07-01

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk YU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US20210074717A1

公开(公告)日：2021-03-11

申请号：US16835484

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon LIM ,  Daeseok BYEON

IPC: H01L27/11575 ,  H01L27/11551 ,  H01L27/11582 ,  H01L27/11548 ,  H01L29/04 ,  H01L27/11519 ,  H01L27/11565

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.